From d49d03846fbdeb5b0a13438251dc326a0e2184e4 Mon Sep 17 00:00:00 2001
From: Maxim Poliakovski <maximumspatium@googlemail.com>
Date: Thu, 30 Nov 2023 11:47:07 +0100
Subject: [PATCH] ppcemu: fix and beatify FPSCR enum.

---
 cpu/ppc/ppcemu.h | 62 ++++++++++++++++++++++++------------------------
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/cpu/ppc/ppcemu.h b/cpu/ppc/ppcemu.h
index a5b66eb..1c28a86 100644
--- a/cpu/ppc/ppcemu.h
+++ b/cpu/ppc/ppcemu.h
@@ -244,37 +244,37 @@ enum CR1_bit : uint32_t {
 };
 
 enum FPSCR : uint32_t {
-    RN = 0x3,
-    NI = 0x4,
-    XE = 0x8,
-    ZE = 0x10,
-    UE = 0x20,
-    OE = 0x40,
-    VE = 0x80,
-    VXCVI = 0x100,
-    VXSQRT = 0x200,
-    VXSOFT = 0x400,
-    FPRF   = 0x1F000,
-    FPCC_FUNAN = 0x10000,
-    FPCC_NEG   = 0x8000,
-    FPCC_POS   = 0x4000,
-    FPCC_ZERO  = 0x2000,
-    FPCC_FPRCD = 0x1000,
-    FI         = 0x20000,
-    FR         = 0x40000,
-    VXVC       = 0x80000,
-    VXIMZ      = 0x100000,
-    VXZDZ      = 0x200000,
-    VXIDI      = 0x400000,
-    VXISI      = 0x800000,
-    VXSNAN     = 0x1000000,
-    XX         = 0x2000000,
-    ZX         = 0x4000000,
-    UX         = 0x8000000,
-    OX         = 0x10000000,
-    VX         = 0x20000000,
-    FEX        = 0x40000000,
-    FX         = 0x80000000
+    RN_MASK     = 0x3,
+    NI          = 1UL << 2,
+    XE          = 1UL << 3,
+    ZE          = 1UL << 4,
+    UE          = 1UL << 5,
+    OE          = 1UL << 6,
+    VE          = 1UL << 7,
+    VXCVI       = 1UL << 8,
+    VXSQRT      = 1UL << 9,
+    VXSOFT      = 1UL << 10,
+    FPCC_FUNAN  = 1UL << 12,
+    FPCC_ZERO   = 1UL << 13,
+    FPCC_POS    = 1UL << 14,
+    FPCC_NEG    = 1UL << 15,
+    FPCC_FPRCD  = 1UL << 16,
+    FPRF_MASK   = FPCC_FPRCD | FPCC_NEG | FPCC_POS | FPCC_ZERO | FPCC_FUNAN,
+    FI          = 1UL << 17,
+    FR          = 1UL << 18,
+    VXVC        = 1UL << 19,
+    VXIMZ       = 1UL << 20,
+    VXZDZ       = 1UL << 21,
+    VXIDI       = 1UL << 22,
+    VXISI       = 1UL << 23,
+    VXSNAN      = 1UL << 24,
+    XX          = 1UL << 25,
+    ZX          = 1UL << 26,
+    UX          = 1UL << 27,
+    OX          = 1UL << 28,
+    VX          = 1UL << 29,
+    FEX         = 1UL << 30,
+    FX          = 1UL << 31
 };
 
 enum MSR : int {