From d843091a4de6b71b26d4d49a06c072fc59bb3008 Mon Sep 17 00:00:00 2001 From: joevt Date: Mon, 22 Aug 2022 02:39:07 -0700 Subject: [PATCH] Allow setting PCI capabilities pointer The capabilities pointer is usually a constant, but whatever the capabilities pointer points to has to be handled by the derived class. --- devices/common/pci/pcidevice.cpp | 3 +++ devices/common/pci/pcidevice.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/devices/common/pci/pcidevice.cpp b/devices/common/pci/pcidevice.cpp index f83257f..32803c5 100644 --- a/devices/common/pci/pcidevice.cpp +++ b/devices/common/pci/pcidevice.cpp @@ -83,6 +83,9 @@ uint32_t PCIDevice::pci_cfg_read(uint32_t reg_offs, uint32_t size) case PCI_CFG_DWORD_15: result = (max_lat << 24) | (min_gnt << 16) | (irq_pin << 8) | irq_line; break; + case PCI_CFG_CAP_PTR: + result = cap_ptr; + break; default: LOG_F( WARNING, "%s: attempt to read from reserved/unimplemented register @%02x.%c", diff --git a/devices/common/pci/pcidevice.h b/devices/common/pci/pcidevice.h index 897a45e..c0184cc 100644 --- a/devices/common/pci/pcidevice.h +++ b/devices/common/pci/pcidevice.h @@ -45,6 +45,8 @@ enum { PCI_CFG_CIS_PTR = 0x28, // Cardbus CIS Pointer PCI_CFG_SUBSYS_ID = 0x2C, // Subsysten IDs PCI_CFG_ROM_BAR = 0x30, // expansion ROM base address + PCI_CFG_CAP_PTR = 0x34, // capabilities pointer + PCI_CFG_DWORD_14 = 0x38, // reserved PCI_CFG_DWORD_15 = 0x3C, // Max_Lat, Min_Gnt, Int_Pin and Int_Line registers }; @@ -117,6 +119,7 @@ protected: uint8_t cache_ln_sz = 0; // cache line size uint16_t subsys_id = 0; uint16_t subsys_vndr = 0; + uint8_t cap_ptr = 0; uint8_t max_lat = 0; uint8_t min_gnt = 0; uint8_t irq_pin = 0;