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https://github.com/dingusdev/dingusppc.git
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53C94: support more registers and commands.
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3258abe190
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@ -26,6 +26,12 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <cinttypes>
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Sc53C94::Sc53C94(uint8_t chip_id)
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{
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this->chip_id = chip_id;
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reset_device();
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}
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void Sc53C94::reset_device()
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{
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// part-unique ID to be read using a magic sequence
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@ -33,18 +39,27 @@ void Sc53C94::reset_device()
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this->clk_factor = 2;
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this->sel_timeout = 0;
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// clear command FIFO
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this->cmd_fifo_pos = 0;
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}
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uint8_t Sc53C94::read(uint8_t reg_offset)
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{
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switch (reg_offset) {
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case Read::Reg53C94::Command:
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return this->cmd_fifo[0];
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case Read::Reg53C94::Status:
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return this->status;
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case Read::Reg53C94::Int_Status:
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return this->int_status;
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case Read::Reg53C94::Xfer_Cnt_Hi:
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if (this->config2 & CFG2_ENF) {
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return (this->xfer_count >> 16) & 0xFFU;
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}
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break;
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default:
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LOG_F(9, "NCR53C94: reading from register %d", reg_offset);
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LOG_F(INFO, "SC53C94: reading from register %d", reg_offset);
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}
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return 0;
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}
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@ -53,7 +68,7 @@ void Sc53C94::write(uint8_t reg_offset, uint8_t value)
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{
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switch (reg_offset) {
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case Write::Reg53C94::Command:
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add_command(value);
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update_command_reg(value);
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break;
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case Write::Reg53C94::Sel_Timeout:
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this->sel_timeout = value;
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@ -75,41 +90,79 @@ void Sc53C94::write(uint8_t reg_offset, uint8_t value)
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}
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}
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void Sc53C94::add_command(uint8_t cmd)
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void Sc53C94::update_command_reg(uint8_t cmd)
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{
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bool is_dma_cmd = !!(cmd & 0x80);
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cmd &= 0x7F;
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if (this->on_reset && cmd != CMD_NOP) {
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if (this->on_reset && (cmd & 0x7F) != CMD_NOP) {
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LOG_F(WARNING, "SC53C94: command register blocked after RESET!");
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return;
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}
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// NOTE: Reset Device (chip), Reset Bus and DMA Stop commands execute
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// immediately while all others are placed into the command FIFO
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switch (cmd & 0x7F) {
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case CMD_RESET_DEVICE:
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case CMD_RESET_BUS:
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case CMD_DMA_STOP:
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this->cmd_fifo_pos = 0; // put them at the bottom of the command FIFO
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}
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if (this->cmd_fifo_pos < 2) {
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// put new command into the command FIFO
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this->cmd_fifo[this->cmd_fifo_pos++] = cmd;
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if (this->cmd_fifo_pos == 1) {
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exec_command();
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}
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} else {
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LOG_F(ERROR, "SC53C94: the top of the command FIFO overwritten!");
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this->status |= 0x40; // signal IOE/Gross Error
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}
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}
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void Sc53C94::exec_command()
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{
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uint8_t cmd = this->cmd_fifo[0] & 0x7F;
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bool is_dma_cmd = !!(this->cmd_fifo[0] & 0x80);
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if (is_dma_cmd) {
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if (this->config2 & CFG2_ENF) { // extended mode: 24-bit
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this->xfer_count = this->set_xfer_count & 0xFFFFFFUL;
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} else { // standard mode: 16-bit
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this->xfer_count = this->set_xfer_count & 0xFFFFUL;
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}
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}
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switch (cmd) {
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case CMD_NOP:
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this->on_reset = false; // unblock the command register
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exec_next_command();
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break;
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case CMD_CLEAR_FIFO:
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this->data_fifo_pos = 0; // set the bottom of the FIFO to zero
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this->data_fifo[0] = 0;
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exec_next_command();
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break;
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case CMD_RESET_DEVICE:
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reset_device();
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this->on_reset = true; // block the command register
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return;
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case CMD_RESET_BUS:
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LOG_F(ERROR, "SC53C94: RESET_BUS command not implemented yet");
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return;
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case CMD_DMA_STOP:
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LOG_F(ERROR, "SC53C94: TARGET_DMA_STOP command not implemented yet");
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return;
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}
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// HACK: commands should be placed into the command FIFO
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if (cmd == CMD_NOP) {
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if (is_dma_cmd) {
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if (this->config2 & CFG2_ENF) { // extended mode: 24-bit
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this->xfer_count = this->set_xfer_count & 0xFFFFFFUL;
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} else { // standard mode: 16-bit
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this->xfer_count = this->set_xfer_count & 0xFFFFUL;
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}
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}
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this->on_reset = false;
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LOG_F(INFO, "SC53C94: resetting SCSI bus...");
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exec_next_command();
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break;
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default:
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LOG_F(ERROR, "SC53C94: invalid/unimplemented command 0x%X", cmd);
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this->cmd_fifo_pos--; // remove invalid command from FIFO
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this->int_status |= 0x40; // set ICMD bit
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}
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}
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void Sc53C94::exec_next_command()
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{
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if (this->cmd_fifo_pos) { // skip empty command FIFO
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this->cmd_fifo_pos--; // remove completed command
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if (this->cmd_fifo_pos) { // is there another command in the FIFO?
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this->cmd_fifo[0] = this->cmd_fifo[1]; // top -> bottom
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exec_command(); // execute it
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}
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}
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}
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@ -39,7 +39,7 @@ namespace Read {
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FIFO = 2,
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Command = 3,
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Status = 4,
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Interrupt = 5,
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Int_Status = 5,
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Seq_Step = 6,
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FIFO_Flags = 7,
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Config_1 = 8,
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@ -72,6 +72,7 @@ namespace Write {
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};
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};
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/** NCR53C94/Am53CF94 commands. */
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enum {
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CMD_NOP = 0,
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CMD_CLEAR_FIFO = 1,
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@ -86,7 +87,7 @@ enum {
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class Sc53C94 {
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public:
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Sc53C94(uint8_t chip_id=12) { this->chip_id = chip_id; };
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Sc53C94(uint8_t chip_id=12);
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~Sc53C94() = default;
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// 53C94 registers access
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@ -95,13 +96,21 @@ public:
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protected:
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void reset_device();
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void add_command(uint8_t cmd);
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void update_command_reg(uint8_t cmd);
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void exec_command();
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void exec_next_command();
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private:
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uint8_t chip_id;
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uint8_t cmd_fifo[2];
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uint8_t data_fifo[16];
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int cmd_fifo_pos;
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int data_fifo_pos;
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bool on_reset = false;
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uint32_t xfer_count;
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uint32_t set_xfer_count;
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uint8_t status;
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uint8_t int_status;
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uint8_t sel_timeout;
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uint8_t clk_factor;
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uint8_t config1;
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