From e3a4539b02e53e3ace887d819fc026b44392d722 Mon Sep 17 00:00:00 2001
From: Maxim Poliakovski <maximumspatium@googlemail.com>
Date: Tue, 3 Aug 2021 16:03:03 +0200
Subject: [PATCH] WIP: Improve MMU emulation documentation.

---
 zdocs/cpu/powerpc/mmu.md    | 23 +++++++++++++++++++++++
 zdocs/cpu/powerpc/mmuemu.md | 12 ++++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 zdocs/cpu/powerpc/mmu.md
 create mode 100644 zdocs/cpu/powerpc/mmuemu.md

diff --git a/zdocs/cpu/powerpc/mmu.md b/zdocs/cpu/powerpc/mmu.md
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+## Disabling BAT translation
+
+BAT translation can be disabled by invalidating BAT registers. This is somewhat CPU specific.
+MPC601 implements its own format for BAT registers that differs from the PowerPC specification.
+
+MPC601-specific lower BAT registers has the "V" bit. If it's cleared, the corresponding BAT pair
+is invalid and won't be used for address translation. To invalidate BATs on MPC601, it's enough
+to write NULL to lower BAT registers. That's exactly what PowerMac 6100 ROM does:
+ ```
+li        r0,     0
+mtspr     ibat0l, r0
+mtspr     ibat1l, r0
+mtspr     ibat2l, r0
+```
+
+PowerPC CPUs starting with 603 uses the BAT register format described in the PowerPC specification.
+The upper BAT registers contain two bits: Vs (supervisor state valid bit) and Vp (problem/user state valid bit).
+PowerPC Architecture First Edition from 1993 gives the following code:
+
+```BAT_entry_valid = (Vs & ~MSR_PR) | (Vp & MSR_PR)```
+
+If neither Vs nor Vp is set, the corresponding BAT pair isn't valid and doesn't participate in address translation.
+To invalidate BATs on non-601, it's sufficient to set the upper BAT register to 0x00000000.
diff --git a/zdocs/cpu/powerpc/mmuemu.md b/zdocs/cpu/powerpc/mmuemu.md
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+# PowerPC Memory Management Unit Emulation
+
+Emulation of a [memory management unit](https://en.wikipedia.org/wiki/Memory_management_unit)
+(MMU) in a full system emulator is considered a hard task. The biggest challenge is to do it fast.
+
+In this article, I'm going to describe a solution for a reasonably fast emulation
+of the PowerPC MMU.
+
+This article is based on ideas presented in the paper "Optimizing Memory Emulation
+in Full System Emulators" by Xin Tong and Motohiro Kawahito (IBM Research Laboratory).
+
+## PowerPC MMU operation