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https://github.com/dingusdev/dingusppc.git
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Direct threaded interpreter (PoC).
This commit is contained in:
Maxim Poliakovski
parent
95fb5d053d
commit
eb338ea886
202
cpu/ppc/dtcinterpreter.cpp
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202
cpu/ppc/dtcinterpreter.cpp
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@ -0,0 +1,202 @@
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#include <cinttypes>
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#include <thirdparty/loguru/loguru.hpp>
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#include "ppcemu.h"
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#include "ppcmmu.h"
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#include "ppcdefs.h"
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#include "jittables.h"
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#include "nuinterpreter.h"
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#if defined(USE_DTC)
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#define CAST(name) &&lab_##name
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struct InterpInstr {
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void* emu_fn;
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InstrInfo info;
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};
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#define REG_D(opcode) ((opcode >> 21) & 0x1F)
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#define REG_A(opcode) ((opcode >> 16) & 0x1F)
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#define REG_B(opcode) ((opcode >> 11) & 0x1F)
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#define REG_S REG_D
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#define BR_BO REG_D
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#define BR_BI REG_A
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#define SIMM(opcode) ((int32_t)((int16_t)(opcode & 0xFFFF)))
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#define UIMM(opcode) ((uint32_t)((uint16_t)(opcode & 0xFFFF)))
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/** mask generator for rotate and shift instructions (§ 4.2.1.4 PowerpC PEM) */
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static inline uint32_t rot_mask(unsigned rot_mb, unsigned rot_me) {
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uint32_t m1 = 0xFFFFFFFFUL >> rot_mb;
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uint32_t m2 = 0xFFFFFFFFUL << (31 - rot_me);
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return ((rot_mb <= rot_me) ? m2 & m1 : m1 | m2);
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}
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CachedInstr code_block[256];
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void NuInterpExec(uint32_t next_pc) {
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/* WARNING: entries in this table MUST be in the same order as constants in PPCInstr! */
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InterpInstr interp_tab[] = {
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{nullptr, {InstrOps::opNone, CFlowType::CFL_NONE, 0}},
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{CAST(addi), {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
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{CAST(adde), {InstrOps::opDAB, CFlowType::CFL_NONE, 1}},
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{CAST(addze), {InstrOps::opDA, CFlowType::CFL_NONE, 1}},
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{CAST(andidot), {InstrOps::opSAUimm, CFlowType::CFL_NONE, 1}},
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{CAST(lwz), {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
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{CAST(lwzu), {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
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{CAST(lbz), {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
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{CAST(lhz), {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
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{CAST(rlwinm), {InstrOps::opRot, CFlowType::CFL_NONE, 1}},
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{CAST(srawidot), {InstrOps::opSASh, CFlowType::CFL_NONE, 1}},
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{CAST(bc), {InstrOps::opBrRel, CFlowType::CFL_COND_BRANCH, 0}},
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{CAST(bdnz), {InstrOps::opBrRel, CFlowType::CFL_COND_BRANCH, 0}},
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{CAST(bdz), {InstrOps::opBrRel, CFlowType::CFL_COND_BRANCH, 0}},
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{CAST(bclr), {InstrOps::opBrLink, CFlowType::CFL_COND_BRANCH, 0}},
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{CAST(mtspr), {InstrOps::opSSpr, CFlowType::CFL_NONE, 2}},
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{CAST(bexit), {InstrOps::opNone, CFlowType::CFL_UNCOND_BRANCH, 0}},
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};
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CachedInstr* c_instr;
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uint32_t opcode, main_opcode;
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unsigned instr_index;
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uint8_t* pc_real;
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bool done;
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pc_real = quickinstruction_translate(next_pc);
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c_instr = &code_block[0];
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done = false;
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while (!done) {
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opcode = ppc_cur_instruction;
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main_opcode = opcode >> 26;
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instr_index = main_index_tab[main_opcode];
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if (!instr_index) {
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switch (main_opcode) {
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case 16:
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instr_index = subgrp16_index_tab[opcode & 3];
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break;
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case 18:
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instr_index = subgrp18_index_tab[opcode & 3];
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break;
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case 19:
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instr_index = subgrp19_index_tab[opcode & 0x7FF];
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break;
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case 31:
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instr_index = subgrp31_index_tab[opcode & 0x7FF];
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break;
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case 59:
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instr_index = subgrp59_index_tab[opcode & 0x3F];
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break;
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case 63:
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instr_index = subgrp63_index_tab[opcode & 0x7FF];
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break;
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default:
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instr_index = 0;
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}
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if (!instr_index) {
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LOG_F(INFO, "Illegal opcode 0x%08X - Program exception!", opcode);
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return;
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}
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}
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const InterpInstr* p_instr = &interp_tab[instr_index];
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c_instr->call_me = p_instr->emu_fn;
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/* pre-decode operands, immediate values etc. */
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switch (p_instr->info.ops_fmt) {
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case InstrOps::opDA:
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c_instr->d1 = REG_D(opcode);
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c_instr->d2 = REG_A(opcode);
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break;
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case InstrOps::opDAB:
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c_instr->d1 = REG_D(opcode);
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c_instr->d2 = REG_A(opcode);
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c_instr->d3 = REG_B(opcode);
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break;
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case InstrOps::opDASimm:
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c_instr->d1 = REG_D(opcode);
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c_instr->d2 = REG_A(opcode);
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c_instr->simm = SIMM(opcode);
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break;
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case InstrOps::opSAUimm:
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c_instr->d1 = REG_S(opcode);
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c_instr->d2 = REG_A(opcode);
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c_instr->uimm = UIMM(opcode);
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break;
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case InstrOps::opSASh:
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c_instr->d1 = REG_S(opcode);
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c_instr->d2 = REG_A(opcode);
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c_instr->d3 = (opcode >> 11) & 0x1F; // shift
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c_instr->uimm = (1 << c_instr->d3) - 1; // mask
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break;
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case InstrOps::opRot:
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c_instr->d1 = REG_S(opcode);
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c_instr->d2 = REG_A(opcode);
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c_instr->d3 = (opcode >> 11) & 0x1F; // shift
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c_instr->d4 = opcode & 1; // Rc bit
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c_instr->uimm = rot_mask((opcode >> 6) & 31, (opcode >> 1) & 31); //mask
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break;
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case InstrOps::opSSpr:
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c_instr->d1 = REG_S(opcode);
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c_instr->uimm = (REG_B(opcode) << 5) | REG_A(opcode);
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break;
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case InstrOps::opBrRel:
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c_instr->bt = SIMM(opcode) >> 2;
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switch (BR_BO(opcode) & 0x1E) {
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case 12:
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case 14:
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c_instr->call_me = interp_tab[PPCInstr::bc].emu_fn;
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c_instr->uimm = 0x80000000UL >> BR_BI(opcode);
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break;
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case 16:
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c_instr->call_me = interp_tab[PPCInstr::bdnz].emu_fn;
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break;
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case 18:
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c_instr->call_me = interp_tab[PPCInstr::bdz].emu_fn;
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break;
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default:
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LOG_F(ERROR, "Unsupported opcode 0x%08X - Program exception!", opcode);
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return;
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}
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break;
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case InstrOps::opBrLink:
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switch (BR_BO(opcode) & 0x1E) {
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case 20: // blr
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c_instr->call_me = interp_tab[PPCInstr::bexit].emu_fn;
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c_instr->uimm = next_pc;
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done = true;
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continue;
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default:
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LOG_F(ERROR, "Unsupported opcode 0x%08X - Program exception!", opcode);
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return;
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}
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break;
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default:
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LOG_F(ERROR, "Unknown opcode format %d!", p_instr->info.ops_fmt);
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return;
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}
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c_instr++;
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next_pc += 4;
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pc_real += 4;
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ppc_set_cur_instruction(pc_real);
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} // while
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//LOG_F(INFO, "PreDecode completed!");
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CachedInstr* code = &code_block[0];
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goto *(code->call_me); // begin code execution
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#define GEN_OP(name,body) lab_##name: { body; }
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#define NEXT goto *((++code)->call_me)
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#include "interpops.h" // auto-generate labeled emulation blocks
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}
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#endif
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@ -90,7 +90,12 @@ GEN_OP(srawidot, {
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GEN_OP(bc, {
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if (ppc_state.cr & code->uimm) {
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#if defined(USE_DTC)
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code += code->bt;
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goto *(code->call_me);
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#else
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interp_tpc += code->bt;
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#endif
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} else {
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NEXT;
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}
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@ -103,7 +108,12 @@ GEN_OP(mtspr, {
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GEN_OP(bdnz, {
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if (--ppc_state.spr[SPR::CTR]) {
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#if defined(USE_DTC)
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code += code->bt;
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goto *(code->call_me);
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#else
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interp_tpc += code->bt;
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#endif
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} else {
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NEXT;
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}
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@ -111,7 +121,12 @@ GEN_OP(bdnz, {
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GEN_OP(bdz, {
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if (!(--ppc_state.spr[SPR::CTR])) {
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#if defined(USE_DTC)
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code += code->bt;
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goto *(code->call_me);
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#else
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interp_tpc += code->bt;
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#endif
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} else {
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NEXT;
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}
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@ -123,5 +138,9 @@ GEN_OP(bclr, {
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GEN_OP(bexit, {
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ppc_state.pc = code->uimm; // write source pc
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#if defined(USE_DTC)
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return;
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#else
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interp_running = false;
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#endif
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})
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@ -6,6 +6,8 @@
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#include "jittables.h"
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#include "nuinterpreter.h"
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#if !defined(USE_DTC)
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CachedInstr* interp_tpc;
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bool interp_running;
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@ -208,3 +210,5 @@ void NuInterpExec(uint32_t start_addr) {
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interp_tpc->call_me(interp_tpc);
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}
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}
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#endif // if !defined(USE_DTC)
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@ -1,12 +1,20 @@
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#ifndef NU_INTERPRETER_H
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#define NU_INTERPRETER_H
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#include "ppcdefs.h"
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#define USE_DTC
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struct CachedInstr; // forward declaration
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typedef void (*ImplSubr)(const CachedInstr *);
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struct CachedInstr {
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#if defined(USE_DTC)
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void* call_me;
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#else
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ImplSubr call_me;
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#endif
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union {
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struct {
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