From f07de5401de9236c65d5ea4de697151a7747a622 Mon Sep 17 00:00:00 2001 From: joevt Date: Tue, 31 Oct 2023 03:37:02 -0700 Subject: [PATCH] sc53c94: Add registers and comments. --- devices/common/scsi/sc53c94.h | 126 ++++++++++++++++++++++------------ 1 file changed, 83 insertions(+), 43 deletions(-) diff --git a/devices/common/scsi/sc53c94.h b/devices/common/scsi/sc53c94.h index ff35d8f..e7d6446 100644 --- a/devices/common/scsi/sc53c94.h +++ b/devices/common/scsi/sc53c94.h @@ -1,6 +1,6 @@ /* DingusPPC - The Experimental PowerPC Macintosh emulator -Copyright (C) 2018-23 divingkatae and maximum +Copyright (C) 2018-24 divingkatae and maximum (theweirdo) spatium (Contact divingkatae#1017 or powermax#2286 on Discord for more info) @@ -43,63 +43,103 @@ class InterruptCtrl; /** 53C94 read registers */ namespace Read { enum Reg53C94 : uint8_t { - Xfer_Cnt_LSB = 0, - Xfer_Cnt_MSB = 1, - FIFO = 2, - Command = 3, - Status = 4, - Int_Status = 5, - Seq_Step = 6, - FIFO_Flags = 7, - Config_1 = 8, - Config_2 = 0xB, - Config_3 = 0xC, - Config_4 = 0xD, // Am53CF94 extension - Xfer_Cnt_Hi = 0xE, // Am53CF94 extension + Xfer_Cnt_LSB = 0, // Current Transfer Count Register LSB + Xfer_Cnt_MSB = 1, // Current Transfer Count Register MSB + FIFO = 2, // FIFO Register + Command = 3, // Command Register + Status = 4, // Status Register + Int_Status = 5, // Interrupt Status Register + Seq_Step = 6, // Internal State Register + FIFO_Flags = 7, // Current FIFO/Internal State Register + Config_1 = 8, // Control Register 1 + // + // + Config_2 = 0xB, // Control Register 2 + Config_3 = 0xC, // Control Register 3 + Config_4 = 0xD, // Control Register 4 + Xfer_Cnt_Hi = 0xE, // Current Transfer Count Register High ; Am53CF94 extension + // }; }; /** 53C94 write registers */ namespace Write { enum Reg53C94 : uint8_t { - Xfer_Cnt_LSB = 0, - Xfer_Cnt_MSB = 1, - FIFO = 2, - Command = 3, - Dest_Bus_ID = 4, - Sel_Timeout = 5, - Sync_Period = 6, - Sync_Offset = 7, - Config_1 = 8, - Clock_Factor = 9, - Test_Mode = 0xA, - Config_2 = 0xB, - Config_3 = 0xC, - Config_4 = 0xD, // Am53CF94 extension - Xfer_Cnt_Hi = 0xE, // Am53CF94 extension - Data_Align = 0xF + Xfer_Cnt_LSB = 0, // Start Transfer Count Register LSB + Xfer_Cnt_MSB = 1, // Start Transfer Count Register MSB + FIFO = 2, // FIFO Register + Command = 3, // Command Register + Dest_Bus_ID = 4, // SCSI Destination ID Register (DID) + Sel_Timeout = 5, // SCSI Timeout Register + Sync_Period = 6, // Synchronous Transfer Period Register + Sync_Offset = 7, // Synchronous Offset Register + Config_1 = 8, // Control Register 1 + Clock_Factor = 9, // Clock Factor Register + Test_Mode = 0xA, // Forced Test Mode Register + Config_2 = 0xB, // Control Register 2 + Config_3 = 0xC, // Control Register 3 + Config_4 = 0xD, // Control Register 4 ; Am53CF94 extension + Xfer_Cnt_Hi = 0xE, // Start Transfer Count Register High ; Am53CF94 extension + Data_Align = 0xF, // Data Alignment Register }; }; /** NCR53C94/Am53CF94 commands. */ enum { - CMD_NOP = 0, - CMD_CLEAR_FIFO = 1, - CMD_RESET_DEVICE = 2, - CMD_RESET_BUS = 3, - CMD_DMA_STOP = 4, - CMD_XFER = 0x10, - CMD_COMPLETE_STEPS = 0x11, - CMD_MSG_ACCEPTED = 0x12, - CMD_SELECT_NO_ATN = 0x41, - CMD_SELECT_WITH_ATN = 0x42, - CMD_ENA_SEL_RESEL = 0x44, + // General Commands + CMD_NOP = 0x00, // no interrupt + CMD_CLEAR_FIFO = 0x01, // no interrupt + CMD_RESET_DEVICE = 0x02, // no interrupt + CMD_RESET_BUS = 0x03, + + // Initiator commands + CMD_XFER = 0x10, + CMD_COMPLETE_STEPS = 0x11, + CMD_MSG_ACCEPTED = 0x12, + //CMD_TRANSFER_PAD_BYTES = 0x18, + CMD_SET_ATN = 0x1A, // no interrupt + //CMD_RESET_ATN = 0x1B, // no interrupt + + // Target commands + //CMD_SEND_MESSAGE = 0x20, + //CMD_SEND_STATUS = 0x21, + //CMD_SEND_DATA = 0x22, + //CMD_DISCONNECT_STEPS = 0x23, + //CMD_TERMINATE_STEPS = 0x24, + //CMD_TARGET_COMMAND_COMPLETE_STEPS = 0x25, + //CMD_DISCONNECT = 0x27, // no interrupt + //CMD_RECEIVE_MESSAGE_STEPS = 0x28, + //CMD_RECEIVE_COMMAND = 0x29, + //CMD_RECEIVE_DATA = 0x2A, + //CMD_RECEIVE_COMMAND_STEPS = 0x2B, + CMD_DMA_STOP = 0x04, // no interrupt + CMD_ACCESS_FIFO_COMMAND = 0x05, + + // Idle Commands + //CMD_RESELECT_STEPS = 0x40, + CMD_SELECT_NO_ATN = 0x41, + CMD_SELECT_WITH_ATN = 0x42, + //CMD_SELECT_WITH_ATN_AND_STOP = 0x43, + CMD_ENA_SEL_RESEL = 0x44, // no interrupt + //CMD_DISABLE_SEL_RESEL = 0x45, + //CMD_SELECT_WITH_ATN3_STEPS = 0x46, + //CMD_RESELECT_WITH_ATN3_STEPS = 0x47, + + // Flags + CMD_OPCODE = 0x7F, + CMD_ISDMA = 0x80, }; /** Status register bits. **/ enum { - STAT_TC = 1 << 4, // Terminal count (NCR) / count to zero (AMD) - STAT_GE = 1 << 6, // Gross Error (NCR) / Illegal Operation Error (AMD) + //SCSI_CTRL_IO = 0x01, // Input/Output + //SCSI_CTRL_CD = 0x02, // Command/Data + //SCSI_CTRL_MSG = 0x04, // Message + //STAT_GCV = 0x08, // Group Code Valid + STAT_TC = 0x10, // Terminal count (NCR) / count to zero (AMD) + //STAT_PE = 0x20, // Parity Error + STAT_GE = 0x40, // Gross Error (NCR) / Illegal Operation Error (AMD) + STAT_INT = 0x80, // Interrupt }; /** Interrupt status register bits. */