From f104a634ea807f68125dde92393509711e63f241 Mon Sep 17 00:00:00 2001 From: Maxim Poliakovski Date: Sun, 26 Sep 2021 14:20:46 +0200 Subject: [PATCH] ppcmmu: some more cleanup. --- cpu/ppc/ppcmmu.cpp | 96 +++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/cpu/ppc/ppcmmu.cpp b/cpu/ppc/ppcmmu.cpp index a869874..8079d1d 100644 --- a/cpu/ppc/ppcmmu.cpp +++ b/cpu/ppc/ppcmmu.cpp @@ -193,7 +193,7 @@ static PATResult page_address_translation(uint32_t la, bool is_instr_fetch, sr_val = ppc_state.sr[(la >> 28) & 0x0F]; if (sr_val & 0x80000000) { - ABORT_F("Direct-store segments not supported, LA=%0xX\n", la); + ABORT_F("Direct-store segments not supported, LA=0x%X\n", la); } /* instruction fetch from a no-execute segment will cause ISI exception */ @@ -253,52 +253,6 @@ static PATResult page_address_translation(uint32_t la, bool is_instr_fetch, }; } -/** PowerPC-style MMU instruction address translation. */ -static uint32_t mmu_instr_translation(uint32_t la) -{ - uint32_t pa; /* translated physical address */ - - bool bat_hit = false; - unsigned msr_pr = !!(ppc_state.msr & 0x4000); - - // Format: %XY - // X - supervisor access bit, Y - problem/user access bit - // Those bits are mutually exclusive - unsigned access_bits = ((msr_pr ^ 1) << 1) | msr_pr; - - for (int bat_index = 0; bat_index < 4; bat_index++) { - PPC_BAT_entry* bat_entry = &ibat_array[bat_index]; - - if ((bat_entry->access & access_bits) && ((la & bat_entry->hi_mask) == bat_entry->bepi)) { - bat_hit = true; - -#ifdef MMU_PROFILING - bat_transl_total++; -#endif - - if (!bat_entry->prot) { - mmu_exception_handler(Except_Type::EXC_ISI, 0x08000000); - } - - // logical to physical translation - pa = bat_entry->phys_hi | (la & ~bat_entry->hi_mask); - break; - } - } - - /* page address translation */ - if (!bat_hit) { - PATResult pat_res = page_address_translation(la, true, msr_pr, 0); - pa = pat_res.phys; - -#ifdef MMU_PROFILING - ptab_transl_total++; -#endif - } - - return pa; -} - /** PowerPC-style MMU data address translation. */ static uint32_t ppc_mmu_addr_translate(uint32_t la, int is_write) { @@ -562,7 +516,7 @@ static TLBEntry* itlb2_refill(uint32_t guest_va) tlb_entry->tag = tag; tlb_entry->flags = flags | TLBFlags::PAGE_MEM; tlb_entry->host_va_offset = (int64_t)reg_desc->mem_ptr - guest_va + - (phys_addr - reg_desc->start); + (phys_addr - reg_desc->start); } else { ABORT_F("Instruction fetch from unmapped memory at 0x%08X!\n", phys_addr); } @@ -1657,6 +1611,52 @@ uint64_t mem_grab_qword(uint32_t addr) { return read_phys_mem(&last_read_area, addr); } +/** PowerPC-style MMU instruction address translation. */ +static uint32_t mmu_instr_translation(uint32_t la) +{ + uint32_t pa; /* translated physical address */ + + bool bat_hit = false; + unsigned msr_pr = !!(ppc_state.msr & 0x4000); + + // Format: %XY + // X - supervisor access bit, Y - problem/user access bit + // Those bits are mutually exclusive + unsigned access_bits = ((msr_pr ^ 1) << 1) | msr_pr; + + for (int bat_index = 0; bat_index < 4; bat_index++) { + PPC_BAT_entry* bat_entry = &ibat_array[bat_index]; + + if ((bat_entry->access & access_bits) && ((la & bat_entry->hi_mask) == bat_entry->bepi)) { + bat_hit = true; + +#ifdef MMU_PROFILING + bat_transl_total++; +#endif + + if (!bat_entry->prot) { + mmu_exception_handler(Except_Type::EXC_ISI, 0x08000000); + } + + // logical to physical translation + pa = bat_entry->phys_hi | (la & ~bat_entry->hi_mask); + break; + } + } + + /* page address translation */ + if (!bat_hit) { + PATResult pat_res = page_address_translation(la, true, msr_pr, 0); + pa = pat_res.phys; + +#ifdef MMU_PROFILING + ptab_transl_total++; +#endif + } + + return pa; +} + uint8_t* quickinstruction_translate(uint32_t addr) { uint8_t* real_addr;