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https://github.com/dingusdev/dingusppc.git
synced 2025-01-11 05:29:43 +00:00
ecowx and eciwx added
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@ -339,6 +339,8 @@ extern void ppc_dcbtst();
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extern void ppc_dcbz();
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extern void ppc_dcbz();
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extern void ppc_divw();
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extern void ppc_divw();
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extern void ppc_divwu();
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extern void ppc_divwu();
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extern void ppc_eciwx();
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extern void ppc_ecowx();
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extern void ppc_eieio();
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extern void ppc_eieio();
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extern void ppc_eqv();
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extern void ppc_eqv();
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extern void ppc_extsb();
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extern void ppc_extsb();
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@ -606,6 +606,9 @@ void initialize_ppc_opcode_tables() {
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SubOpcode31Grabber[918] = ppc_sthbrx;
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SubOpcode31Grabber[918] = ppc_sthbrx;
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SubOpcode31Grabber[983] = ppc_stfiwx;
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SubOpcode31Grabber[983] = ppc_stfiwx;
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SubOpcode31Grabber[310] = ppc_eciwx;
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SubOpcode31Grabber[438] = ppc_ecowx;
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SubOpcode31Grabber[24] = ppc_slw;
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SubOpcode31Grabber[24] = ppc_slw;
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SubOpcode31Grabber[28] = ppc_and;
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SubOpcode31Grabber[28] = ppc_and;
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SubOpcode31Grabber[60] = ppc_andc;
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SubOpcode31Grabber[60] = ppc_andc;
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@ -909,17 +909,17 @@ void dppc_interpreter::ppc_mtspr() {
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void dppc_interpreter::ppc_mftb() {
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void dppc_interpreter::ppc_mftb() {
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uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 31) << 5) | ((ppc_cur_instruction >> 16) & 31);
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uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 31) << 5) | ((ppc_cur_instruction >> 16) & 31);
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reg_d = (ppc_cur_instruction >> 21) & 31;
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reg_d = (ppc_cur_instruction >> 21) & 31;
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switch (ref_spr) {
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switch (ref_spr) {
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case 268:
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case 268:
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ppc_state.gpr[reg_d] = timebase_counter & 0xFFFFFFFFUL;
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ppc_state.gpr[reg_d] = timebase_counter & 0xFFFFFFFFUL;
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break;
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break;
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case 269:
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case 269:
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ppc_state.gpr[reg_d] = (timebase_counter >> 32) & 0xFFFFFFFFUL;
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ppc_state.gpr[reg_d] = (timebase_counter >> 32) & 0xFFFFFFFFUL;
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break;
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break;
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default:
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default:
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std::cout << "Invalid TBR access attempted!" << std::endl;
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LOG_F(ERROR, "Invalid TBR access attempted !\n");
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}
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}
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}
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}
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void dppc_interpreter::ppc_mtcrf() {
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void dppc_interpreter::ppc_mtcrf() {
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@ -2096,6 +2096,46 @@ void dppc_interpreter::ppc_stswx() {
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}
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}
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}
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}
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void dppc_interpreter::ppc_eciwx() {
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uint32_t ear_enable = 0x80000000;
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// error if EAR[E] != 1
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if (!(ppc_state.spr[282] && ear_enable)) {
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ppc_exception_handler(Except_Type::EXC_DSI, 0x0);
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}
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ppc_grab_regsdab();
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ppc_effective_address = (reg_a == 0) ? ppc_result_b : (ppc_result_a + ppc_result_b);
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if (ppc_effective_address & 0x3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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}
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ppc_result_d = mmu_read_vmem<uint32_t>(ppc_effective_address);
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ppc_store_result_regd();
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}
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void dppc_interpreter::ppc_ecowx() {
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uint32_t ear_enable = 0x80000000;
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// error if EAR[E] != 1
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if (!(ppc_state.spr[282] && ear_enable)) {
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ppc_exception_handler(Except_Type::EXC_DSI, 0x0);
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}
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ppc_grab_regssab();
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ppc_effective_address = (reg_a == 0) ? ppc_result_b : (ppc_result_a + ppc_result_b);
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if (ppc_effective_address & 0x3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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}
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mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
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ppc_store_result_regd();
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}
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// TLB Instructions
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// TLB Instructions
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void dppc_interpreter::ppc_tlbie() {
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void dppc_interpreter::ppc_tlbie() {
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@ -2111,6 +2151,9 @@ void dppc_interpreter::ppc_tlbia() {
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num_supervisor_instrs++;
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num_supervisor_instrs++;
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#endif
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#endif
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/* placeholder */
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/* placeholder */
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if (ppc_state.spr[SPR::PVR] == PPC_VER::MPC601) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, 0x0);
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}
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}
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}
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void dppc_interpreter::ppc_tlbld() {
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void dppc_interpreter::ppc_tlbld() {
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@ -2132,4 +2175,7 @@ void dppc_interpreter::ppc_tlbsync() {
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num_supervisor_instrs++;
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num_supervisor_instrs++;
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#endif
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#endif
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/* placeholder */
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/* placeholder */
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if (ppc_state.spr[SPR::PVR] == PPC_VER::MPC601) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, 0x0);
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}
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}
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}
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