From fc3901676b36ee0282449a3aeb562d96f771750c Mon Sep 17 00:00:00 2001 From: Maxim Poliakovski Date: Sun, 13 Mar 2022 21:00:16 +0100 Subject: [PATCH] Heathrow: use common PCI configuration code. --- devices/ioctrl/heathrow.cpp | 67 ++++++++++++++++++++++++------------- devices/ioctrl/macio.h | 43 +++++++----------------- 2 files changed, 55 insertions(+), 55 deletions(-) diff --git a/devices/ioctrl/heathrow.cpp b/devices/ioctrl/heathrow.cpp index 6c38bde..0e70167 100644 --- a/devices/ioctrl/heathrow.cpp +++ b/devices/ioctrl/heathrow.cpp @@ -1,6 +1,6 @@ /* DingusPPC - The Experimental PowerPC Macintosh emulator -Copyright (C) 2018-21 divingkatae and maximum +Copyright (C) 2018-22 divingkatae and maximum (theweirdo) spatium (Contact divingkatae#1017 or powermax#2286 on Discord for more info) @@ -43,9 +43,22 @@ along with this program. If not, see . using namespace std; -HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow") { +HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow"), InterruptCtrl() +{ supports_types(HWCompType::MMIO_DEV | HWCompType::INT_CTRL); + // populate my PCI config header + this->vendor_id = PCI_VENDOR_APPLE; + this->device_id = 0x0010; + this->class_rev = 0xFF000001; + this->cache_ln_sz = 8; + this->lat_timer = 0x40; + this->bars_cfg[0] = 0xFFF80000UL; // declare 512Kb of memory-mapped I/O space + + this->pci_notify_bar_change = [this](int bar_num) { + this->notify_bar_change(bar_num); + }; + this->nvram = std::unique_ptr (new NVram()); this->viacuda = std::unique_ptr (new ViaCuda()); @@ -65,30 +78,18 @@ HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow") { this->swim3 = std::unique_ptr (new Swim3::Swim3Ctrl()); } -uint32_t HeathrowIC::pci_cfg_read(uint32_t reg_offs, uint32_t size) { - return this->pci_cfg_hdr[reg_offs & 0xFF]; -} +void HeathrowIC::notify_bar_change(int bar_num) +{ + if (bar_num) // only BAR0 is supported + return; -void HeathrowIC::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size) { - switch (reg_offs) { - case CFG_REG_BAR0: // base address register - value = LE2BE(value); - if (value == 0xFFFFFFFF) { - LOG_F( - ERROR, - "%s err: BAR0 block size determination not \ - implemented yet \n", - this->name.c_str()); - } else if (value & 1) { - LOG_F(ERROR, "%s err: BAR0 I/O space not supported! \n", this->name.c_str()); - } else if (value & 0x06) { - LOG_F(ERROR, "%s err: BAR0 64-bit I/O space not supported! \n", this->name.c_str()); - } else { - this->base_addr = value & 0xFFF80000; - this->host_instance->pci_register_mmio_region(this->base_addr, 0x80000, this); - LOG_F(INFO, "%s base address set to %x \n", this->name.c_str(), this->base_addr); + if (this->base_addr != (this->bars[bar_num] & 0xFFFFFFF0UL)) { + if (this->base_addr) { + LOG_F(WARNING, "Heathrow: deallocating I/O memory not implemented"); } - break; + this->base_addr = this->bars[0] & 0xFFFFFFF0UL; + this->host_instance->pci_register_mmio_region(this->base_addr, 0x80000, this); + LOG_F(INFO, "%s: base address set to 0x%X", this->pci_name.c_str(), this->base_addr); } } @@ -302,3 +303,21 @@ void HeathrowIC::feature_control(const uint32_t value) LOG_F(9, "Heathrow: Monitor sense disabled"); } } + +uint32_t HeathrowIC::register_dev_int(IntSrc src_id) +{ + return 0; +} + +uint32_t HeathrowIC::register_dma_int(IntSrc src_id) +{ + return 0; +} + +void HeathrowIC::ack_int(uint32_t irq_id, uint8_t irq_line_state) +{ +} + +void HeathrowIC::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state) +{ +} diff --git a/devices/ioctrl/macio.h b/devices/ioctrl/macio.h index fcbbcc3..dfb0cf0 100644 --- a/devices/ioctrl/macio.h +++ b/devices/ioctrl/macio.h @@ -92,23 +92,21 @@ along with this program. If not, see . VIA-CUDA register space: 0x00016000, size: 0x00002000 */ -class HeathrowIC : public PCIDevice { +class HeathrowIC : public PCIDevice, public InterruptCtrl { public: HeathrowIC(); ~HeathrowIC() = default; - /* PCI device methods */ - bool supports_io_space(void) { - return false; - }; - - uint32_t pci_cfg_read(uint32_t reg_offs, uint32_t size); - void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size); - - /* MMIO device methods */ + // MMIO device methods uint32_t read(uint32_t reg_start, uint32_t offset, int size); void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); + // InterruptCtrl methods + uint32_t register_dev_int(IntSrc src_id); + uint32_t register_dma_int(IntSrc src_id); + void ack_int(uint32_t irq_id, uint8_t irq_line_state); + void ack_dma_int(uint32_t irq_id, uint8_t irq_line_state); + protected: uint32_t dma_read(uint32_t offset, int size); void dma_write(uint32_t offset, uint32_t value, int size); @@ -116,29 +114,12 @@ protected: uint32_t mio_ctrl_read(uint32_t offset, int size); void mio_ctrl_write(uint32_t offset, uint32_t value, int size); + void notify_bar_change(int bar_num); + void feature_control(const uint32_t value); private: - uint8_t pci_cfg_hdr[256] = { - 0x6B, - 0x10, // vendor ID: Apple Computer Inc. - 0x10, - 0x00, // device ID: Heathrow Mac I/O - 0x00, - 0x00, // PCI command (set to 0 at power-up?) - 0x00, - 0x00, // PCI status (set to 0 at power-up?) - 0x01, // revision ID - // class code is reported in OF property "class-code" as 0xff0000 - 0x00, // standard programming - 0x00, // subclass code - 0xFF, // class code: unassigned - 0x00, - 0x00, // unknown defaults - 0x00, - 0x00 // unknown defaults - }; - + uint32_t base_addr = 0; uint32_t int_mask2 = 0; uint32_t int_clear2 = 0; uint32_t int_levels2 = 0; @@ -157,7 +138,7 @@ private: std::unique_ptr escc; // ESCC serial controller std::unique_ptr swim3; // floppy disk controller - std::unique_ptr snd_out_dma; + std::unique_ptr snd_out_dma; }; #endif /* MACIO_H */