joevt
f5dbb4fa43
macio: Add more names for feature control bits.
2026-07-24 20:58:21 -07:00
dingusdev
79f1edc102
Adding additional regs in AMIC
2026-07-24 20:58:04 -07:00
Tim Jarzombek and joevt
3ecf59233c
amic: Make RcvDma fields unique_ptr like XmitDma.
...
From earlier commit:
"amic: Emulate SCC receive DMA registers instead of returning random
values."
Co-Authored-By: joevt <joevt@shaw.ca >
2026-07-24 07:44:02 -07:00
joevt
baeed79f12
amic: Add all the SCC DMA registers.
2026-07-23 20:56:53 -07:00
joevt
2a3b6d9cb7
dmacore: Rename is_ready.
...
So that it is not confused with other contexts.
2026-07-14 18:48:10 -07:00
Maxim Poliakovski
b81920fcb2
maciotwo: remove everything related to EMMO.
...
EMMO should be activated in the particular machine expert
because the location of that bit is board specific.
2026-07-07 13:38:52 +02:00
Maxim Poliakovski
9e70b3ce3f
macio.h: remove board specific definitions.
2026-07-04 23:35:12 +02:00
Maxim Poliakovski
398ab2f7f6
maciobase: common support for IOBus devices.
2026-07-04 18:21:41 +02:00
joevt
37da4d3162
dmacore: Add DmaPushResult.
2026-07-02 08:10:04 -07:00
Maxim Poliakovski
9561edcea2
sc53c94: remove obsolete DMA code.
2026-07-01 19:56:15 +02:00
Maxim Poliakovski
ba34d78a7c
grandcentral: fix interrupt clearing.
...
Fix an issue introduced in 4d9f6f33ee
2026-07-01 19:56:15 +02:00
Maxim Poliakovski
4d9f6f33ee
maciotwo: support partial writes to the control registers.
2026-06-21 22:14:09 +02:00
Maxim Poliakovski
d8aa33f207
macio.h: add definition for Entry Systems Support register.
...
Rename and document MIO_AUX_CTL register as well.
2026-06-21 13:45:36 +02:00
Maxim Poliakovski
293f594cdc
maciotwo: support partial/spanning reads from control registers.
2026-06-21 02:28:25 +02:00
joevt
a3c6d25cc5
grandcentral: Improve IOBus device 3/5 comments.
2026-06-17 07:02:12 -07:00
Maxim Poliakovski
0e2ffa7863
Move endianswap.h to core/*
2026-06-07 21:10:51 +02:00
Maxim Poliakovski
a68bd5b07e
escc: switch to new DMA API.
2026-05-29 23:36:24 +02:00
Maxim Poliakovski
30d95e1409
dmacore: add support for several channels per device.
2026-05-29 23:22:16 +02:00
Maxim Poliakovski
41f4af948f
grandcentral: implement DMA interrupt clearing.
2026-05-29 21:22:56 +02:00
Maxim Poliakovski
60825ce664
maciotwo: add dispatchers for the ESCC A DMA channels.
2026-05-29 18:14:08 +02:00
Maxim Poliakovski
ee1b1dd873
maciotwo: clear DMA interrupt flags.
2026-05-29 17:48:55 +02:00
Maxim Poliakovski
3c1308d006
maciobase: implement DMA interrupt clearing.
2026-05-29 17:21:08 +02:00
joevt
a8dfc8d15c
grandcentral: Decode entire DMA range.
...
Only DMA channels 0..0xA actually exist, but the range extends to 0x7F.
2026-05-27 06:43:40 -07:00
Maxim Poliakovski
3f6f05694f
maciotwo: add dispatchers for the ESCC B DMA channels.
2026-05-18 14:14:58 +02:00
Maxim Poliakovski
1b3a6b062c
maciotwo: prevent logging when writing to MIO_INT_LEVELS1.
2026-05-03 14:59:04 +02:00
Maxim Poliakovski
f0bb36b9da
maciotwo: add Valkyrie interrupt registration.
2026-05-03 13:40:40 +02:00
Maxim Poliakovski
c385b131d7
macio.h: remove documentation comment.
...
It has already been moved to zdocs/developers/heathrow.md
2026-05-03 13:07:12 +02:00
Tim Jarzombek
ad4515721b
amic: Emulate SCC receive DMA registers instead of returning random values.
...
The SCC DMA Receive control registers previously returned std::rand(),
a workaround to unblock Mac OS 8.5/8.5.1 boot which polls these
registers expecting specific bit patterns. This caused non-deterministic
bimodal boot times (~10s vs ~18s) on Power Mac 6100 as the guest would
sometimes enter a ~7s polling loop depending on the random value.
Add AmicSerialRcvDma to properly track the control register and byte
count state for both SCC receive channels. Writes now update the status
byte using the same bit manipulation as the transmit DMA channels, and
reads return the tracked state. Also wire up the RX byte count registers
(SCC_RXA/B_Byte_Cnt_Hi/Lo) which were previously ignored on write.
2026-03-08 18:34:00 -07:00
joevt
16117e6c60
escc: Add channel and direction enums.
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Also fix dma_ch index in dma_out_tx, dma_flush_tx.
2026-03-08 10:54:09 -07:00
dingusdev
213dd4c16e
Update copyright info further
2026-01-30 08:12:04 -07:00
Maxim Poliakovski
e75ee8d32a
Update copyright year.
2026-01-30 12:15:00 +01:00
joevt
d693b0f443
maciotwo: Fix IDE read/write mask again.
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Use the entire 4K range.
2026-01-20 07:07:11 -07:00
joevt
5c646e8270
maciotwo: Add methods to override OHARE_ID ids.
2026-01-17 08:40:45 -07:00
joevt
65c5d2425e
maciotwo: Fix IDE read/write mask.
2026-01-17 07:02:06 -07:00
joevt
f2676e0324
maciotwo: Make Ide1 optional.
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Some Macs that use OHare do not have a second ATA bus exposed by Open
Firmware. Allow Ide1 to not be included.
# Conflicts:
# devices/ioctrl/maciotwo.cpp
2026-01-17 06:54:44 -07:00
Maxim Poliakovski
5996358308
maciotwo: initialize and connect IDE DMA channels.
2026-01-02 21:30:21 +01:00
joevt
678b51ddfb
grandcentral: Add comment.
2025-11-28 18:18:00 +01:00
Maxim Poliakovski
a7deca1228
maciotwo: add DMA channels for IDE0 and IDE1.
2025-11-16 20:16:30 +01:00
Maxim Poliakovski
8230223440
maciotwo: remove obsolete debugging stuff.
2025-11-10 18:04:52 +01:00
joevt
c7fbd5ed4a
grandcentral: Fix DEVSEL.
2025-11-10 07:40:34 -07:00
dingusdev
fb5f1ed915
Stub out serial
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Allows Mac OS 8.x and 9.x to boot from HD on older PCI Power Macs
2025-08-24 13:52:09 -07:00
joevt
d789935a6d
grandcentral: Supports IOBUS_HOST comp type.
2025-08-24 13:46:03 -07:00
joevt
63be7f318e
macio: Add TAM note.
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Setting this bit for Gazelle causes Twentieth Anniversary Mac startup
chime.
2025-07-07 19:41:52 -07:00
Maxim Poliakovski
91cb5fc6ad
maciotwo: change OHare MESH cell to MeshTnt.
...
It looks like the MESH cell inside OHare reports its version
in the old format, i.e. 0xEY where Y is >= 1.
Returning MESH ID in the new (Heathrow) format causes
the Native SCSI Manager to misrecognize the HW and crash badly.
2025-06-30 01:48:40 +02:00
joevt
5412fbc198
Remove superfluous semicolons.
2025-06-27 19:01:14 -07:00
Maxim Poliakovski
b351b578b7
maciotwo.cpp: remove superfluous mesh_dma checks.
2025-06-22 13:02:28 +02:00
joevt
1fae4d28ac
maciotwo: Standardize log message format.
2025-06-22 12:16:40 +02:00
joevt
881c0f7d4e
maciotwo: Add interrupts for OHare part 2.
2025-06-22 12:16:40 +02:00
joevt
4a824cd9aa
maciotwo: Fix indent part 2.
2025-06-22 12:16:40 +02:00
joevt
33e351926f
maciotwo: Add interrupts for OHare.
2025-06-22 12:16:40 +02:00
joevt
dingusdev
Tim Jarzombekandjoevt
Maxim Poliakovski