joevt
e1e324b5d8
maciotwo: Apply mask when reading int events.
...
The event is still pending even if masked. It will cause an interrupt
when it is unmasked unless it is cleared. Tested on real B&W G3.
2026-09-03 07:37:00 -07:00
Maxim Poliakovski
b81920fcb2
maciotwo: remove everything related to EMMO.
...
EMMO should be activated in the particular machine expert
because the location of that bit is board specific.
2026-07-07 13:38:52 +02:00
Maxim Poliakovski
4d9f6f33ee
maciotwo: support partial writes to the control registers.
2026-06-21 22:14:09 +02:00
Maxim Poliakovski
d8aa33f207
macio.h: add definition for Entry Systems Support register.
...
Rename and document MIO_AUX_CTL register as well.
2026-06-21 13:45:36 +02:00
Maxim Poliakovski
293f594cdc
maciotwo: support partial/spanning reads from control registers.
2026-06-21 02:28:25 +02:00
Maxim Poliakovski
60825ce664
maciotwo: add dispatchers for the ESCC A DMA channels.
2026-05-29 18:14:08 +02:00
Maxim Poliakovski
ee1b1dd873
maciotwo: clear DMA interrupt flags.
2026-05-29 17:48:55 +02:00
Maxim Poliakovski
3f6f05694f
maciotwo: add dispatchers for the ESCC B DMA channels.
2026-05-18 14:14:58 +02:00
Maxim Poliakovski
1b3a6b062c
maciotwo: prevent logging when writing to MIO_INT_LEVELS1.
2026-05-03 14:59:04 +02:00
Maxim Poliakovski
f0bb36b9da
maciotwo: add Valkyrie interrupt registration.
2026-05-03 13:40:40 +02:00
dingusdev
213dd4c16e
Update copyright info further
2026-01-30 08:12:04 -07:00
Maxim Poliakovski
e75ee8d32a
Update copyright year.
2026-01-30 12:15:00 +01:00
joevt
d693b0f443
maciotwo: Fix IDE read/write mask again.
...
Use the entire 4K range.
2026-01-20 07:07:11 -07:00
joevt
65c5d2425e
maciotwo: Fix IDE read/write mask.
2026-01-17 07:02:06 -07:00
joevt
f2676e0324
maciotwo: Make Ide1 optional.
...
Some Macs that use OHare do not have a second ATA bus exposed by Open
Firmware. Allow Ide1 to not be included.
# Conflicts:
# devices/ioctrl/maciotwo.cpp
2026-01-17 06:54:44 -07:00
Maxim Poliakovski
5996358308
maciotwo: initialize and connect IDE DMA channels.
2026-01-02 21:30:21 +01:00
Maxim Poliakovski
a7deca1228
maciotwo: add DMA channels for IDE0 and IDE1.
2025-11-16 20:16:30 +01:00
Maxim Poliakovski
8230223440
maciotwo: remove obsolete debugging stuff.
2025-11-10 18:04:52 +01:00
dingusdev
fb5f1ed915
Stub out serial
...
Allows Mac OS 8.x and 9.x to boot from HD on older PCI Power Macs
2025-08-24 13:52:09 -07:00
Maxim Poliakovski
91cb5fc6ad
maciotwo: change OHare MESH cell to MeshTnt.
...
It looks like the MESH cell inside OHare reports its version
in the old format, i.e. 0xEY where Y is >= 1.
Returning MESH ID in the new (Heathrow) format causes
the Native SCSI Manager to misrecognize the HW and crash badly.
2025-06-30 01:48:40 +02:00
Maxim Poliakovski
b351b578b7
maciotwo.cpp: remove superfluous mesh_dma checks.
2025-06-22 13:02:28 +02:00
joevt
1fae4d28ac
maciotwo: Standardize log message format.
2025-06-22 12:16:40 +02:00
joevt
881c0f7d4e
maciotwo: Add interrupts for OHare part 2.
2025-06-22 12:16:40 +02:00
joevt
4a824cd9aa
maciotwo: Fix indent part 2.
2025-06-22 12:16:40 +02:00
joevt
33e351926f
maciotwo: Add interrupts for OHare.
2025-06-22 12:16:40 +02:00
joevt
3f57d072ec
maciotwo: Fix indent.
2025-06-22 12:16:40 +02:00
joevt
0f17a04b2f
maciotwo: Fix grammar.
2025-06-20 07:03:04 -07:00
Maxim Poliakovski
6b50f85bfc
Switch to MacIoTwo's OHare.
2025-06-17 16:17:11 +02:00
Maxim Poliakovski
157bd6de88
Switch to MacIoTwo's Heathrow.
2025-06-17 15:52:46 +02:00
Maxim Poliakovski
53eafa5f24
New class MacIoTwo for OHare/Heathrow/Paddington emulation.
2025-06-17 15:27:48 +02:00
joevt
Maxim Poliakovski
dingusdev