amic: Add more registers.

This register is used in the control ndrv to detect presence of connected S-Video or composite video display.

devices/common/dbdma.cpp

@@ -21,6 +21,7 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 /** @file Descriptor-based direct memory access emulation. */
 
+#include <core/timermanager.h>
 #include <cpu/ppc/ppcmmu.h>
 #include <devices/common/dbdma.h>
 #include <devices/common/dmacore.h>
@@ -261,9 +262,11 @@ void DMAChannel::update_irq() {
                 }
             }
             if (cond) {
-                if (int_ctrl)
-                    this->int_ctrl->ack_dma_int(this->irq_id, 1);
-                else
+                if (int_ctrl) {
+                    TimerManager::get_instance()->add_immediate_timer([this] {
+                        this->int_ctrl->ack_dma_int(this->irq_id, 1);
+                    });
+                } else
                     LOG_F(ERROR, "%s Interrupt ignored", this->get_name().c_str());
             }
         }

devices/common/scsi/scsihd.cpp

@@ -269,7 +269,17 @@ void ScsiHardDisk::inquiry() {
         LOG_F(INFO, "%s: %d bytes requested in INQUIRY", this->name.c_str(), alloc_len);
     }
 
-    this->data_buf[0] =    0; // device type: Direct-access block device
+    int lun;
+    if (this->last_selection_has_atention) {
+        LOG_F(INFO, "%s: INQUIRY (%d bytes) with ATN LUN = %02x & 7", this->name.c_str(), alloc_len, this->last_selection_message);
+        lun = this->last_selection_message & 7;
+    }
+    else {
+        LOG_F(INFO, "%s: INQUIRY (%d bytes) with NO ATN LUN = %02x >> 5", this->name.c_str(), alloc_len, cmd_buf[1]);
+        lun = cmd_buf[1] >> 5;
+    }
+
+    this->data_buf[0] = (lun == this->lun) ? 0 : 0x7f; // device type: Direct-access block device (hard drive)
     this->data_buf[1] =    0; // non-removable media; 0x80 = removable media
     this->data_buf[2] =    2; // ANSI version: SCSI-2
     this->data_buf[3] =    1; // response data format

devices/ioctrl/amic.h

@@ -219,8 +219,10 @@ enum AMICReg : uint32_t {
     Ariel_Config        = 0x24002,
 
     // VIA2 registers
+    //                  = 0x26000,
     VIA2_Slot_IFR       = 0x26002,
     VIA2_IFR            = 0x26003,
+    //                  = 0x26010,
     VIA2_Slot_IER       = 0x26012,
     VIA2_IER            = 0x26013,
     VIA2_IFR_RBV        = 0x27A03, // RBV-compatible mirror for the VIA2_IFR
@@ -266,8 +268,12 @@ enum AMICReg : uint32_t {
     Floppy_DMA_Ctrl     = 0x32068,
 
     SCC_DMA_Xmt_A_Ctrl  = 0x32088,
+    SCC_RXA_Byte_Cnt_Hi = 0x32094, // 5 bits, read-only
+    SCC_RXA_Byte_Cnt_Lo = 0x32095, // 8 bits, read-only
     SCC_DMA_Rcv_A_Ctrl  = 0x32098,
     SCC_DMA_Xmt_B_Ctrl  = 0x320A8,
+    SCC_RXB_Byte_Cnt_Hi = 0x320B4, // 5 bits, read-only
+    SCC_RXB_Byte_Cnt_Lo = 0x320B5, // 8 bits, read-only
     SCC_DMA_Rcv_B_Ctrl  = 0x320B8,
 };
 

devices/ioctrl/grandcentral.cpp

@@ -107,7 +107,7 @@ GrandCentral::GrandCentral() : PCIDevice("mac-io/grandcentral"), InterruptCtrl()
     this->escc->set_dma_channel(3, this->escc_b_rx_dma.get());
 
     // connect MESH (internal SCSI)
-    this->mesh = dynamic_cast<MeshController*>(gMachineObj->get_comp_by_name("MeshTnt"));
+    this->mesh = dynamic_cast<MeshController*>(gMachineObj->get_comp_by_name_optional("MeshTnt"));
     if (this->mesh == nullptr) {
         LOG_F(WARNING, "%s: Mesh not found, using MeshStub instead", this->name.c_str());
         this->mesh_stub = std::unique_ptr<MeshStub>(new MeshStub());
@@ -185,7 +185,10 @@ uint32_t GrandCentral::read(uint32_t rgn_start, uint32_t offset, int size)
         case 7: // VIA-CUDA
             return this->viacuda->read((offset >> 9) & 0xF);
         case 8: // MESH SCSI
-            return this->mesh->read((offset >> 4) & 0xF);
+            if (this->mesh)
+                return this->mesh->read((offset >> 4) & 0xF);
+            else if (this->mesh_stub)
+                return this->mesh_stub->read((offset >> 4) & 0xF);
         case 9: // ENET-ROM
             return ENET_ROM[(offset >> 4) & 0x7];
         case 0xA: // IOBus device #1 ; Board register 1 and bandit1 PRSNT bits
@@ -232,7 +235,11 @@ uint32_t GrandCentral::read(uint32_t rgn_start, uint32_t offset, int size)
             //LOG_F(WARNING, "%s: Unsupported DMA channel DMA_AUDIO_IN read  @%02x.%c", this->name.c_str(), offset & 0xFF, SIZE_ARG(size));
             return 0; // this->snd_in_dma->reg_read(offset & 0xFF, size);
         case MIO_GC_DMA_SCSI_MESH:
-            return this->mesh_dma->reg_read(offset & 0xFF, size);
+            if (this->mesh_dma) {
+                return this->mesh_dma->reg_read(offset & 0xFF, size);
+                break;
+            }
+            // fallthrough
         default:
             LOG_F(WARNING, "%s: unimplemented DMA register at 0x%X",
                   this->name.c_str(), this->base_addr + offset);
@@ -289,7 +296,10 @@ void GrandCentral::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in
             this->viacuda->write((offset >> 9) & 0xF, value);
             break;
         case 8: // MESH SCSI
-            this->mesh->write((offset >> 4) & 0xF, value);
+            if (this->mesh)
+                this->mesh->write((offset >> 4) & 0xF, value);
+            else if (this->mesh_stub)
+                this->mesh_stub->write((offset >> 4) & 0xF, value);
             break;
         case 0xA: // IOBus device #1 ; Board register 1 and bandit1 PRSNT bits
         case 0xB: // IOBus device #2 ; RaDACal/DACula
@@ -348,8 +358,11 @@ void GrandCentral::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in
             //this->snd_in_dma->reg_write(offset & 0xFF, value, size);
             break;
         case MIO_GC_DMA_SCSI_MESH:
-            this->mesh_dma->reg_write(offset & 0xFF, value, size);
-            break;
+            if (this->mesh_dma) {
+                this->mesh_dma->reg_write(offset & 0xFF, value, size);
+                break;
+            }
+            // fallthrough
         default:
             LOG_F(WARNING, "%s: unimplemented DMA register at 0x%X",
                   this->name.c_str(), this->base_addr + offset);

devices/ioctrl/macio.h

@@ -83,7 +83,10 @@ enum {
     MIO_INT_EVENTS1 = 0x20,
     MIO_INT_MASK1   = 0x24,
     MIO_INT_CLEAR1  = 0x28,
-    MIO_INT_LEVELS1 = 0x2C
+    MIO_INT_LEVELS1 = 0x2C,
+
+    MIO_FATMAN_FLAGS = 0x34,
+    // 0x300000 bits for composite/s-video connected displays (1 = disconnected)
 };
 
 class IobusDevice {
@@ -183,7 +186,7 @@ private:
     Swim3::Swim3Ctrl*   swim3;      // floppy disk controller
 
     std::unique_ptr<DMAChannel>     curio_dma;
-    std::unique_ptr<DMAChannel>     mesh_dma;
+    std::unique_ptr<DMAChannel>     mesh_dma = nullptr;
     std::unique_ptr<DMAChannel>     snd_out_dma;
     std::unique_ptr<DMAChannel>     snd_in_dma;
     std::unique_ptr<DMAChannel>     floppy_dma;

devices/memctrl/platinum.cpp

@@ -444,6 +444,13 @@ void PlatinumCtrl::enable_display() {
 
     this->stop_refresh_task();
 
+    if (this->active_width <= 0 || this->active_height <= 0 || this->pixel_clock <= 0) {
+        this->blank_on = true;
+        this->crtc_on = false;
+        this->blank_display();
+        return;
+    }
+
     this->refresh_rate = (double)(this->pixel_clock) / (this->hori_total * this->vert_total);
     this->start_refresh_task();
 

devices/video/control.h

@@ -47,20 +47,20 @@ enum ControlRegs : int {
     VBPEQ           = 0x05, // vertical back porch with EQ      (rw) 12 bits
     VSYNC           = 0x06, // vertical sync starting point     (rw) 12 bits
     VHLINE          = 0x07, // vertical half line               (rw) 12 bits
-    PIPE_DELAY      = 0x08, // controls pixel pipe delay        (rw) 12 bits
+    PIPE_DELAY      = 0x08, // controls pixel pipe delay        (rw) 10 bits, ndrv says 12 bits but only 10 are writable
     HPIX            = 0x09, // horizontal pixel count           (rw) 12 bits
     HFP             = 0x0A, // horizontal front porch           (rw) 12 bits
     HAL             = 0x0B, // horizontal active line           (rw) 12 bits
     HBWAY           = 0x0C, // horizontal breezeway             (rw) 12 bits
     HSP             = 0x0D, // horizontal sync starting point   (rw) 12 bits
-    HEQ             = 0x0E, // horizontal equalization          (rw) 12 bits
+    HEQ             = 0x0E, // horizontal equalization          (rw)  8 bits, ndrv says 12 bits but only 8 are writable
     HLFLN           = 0x0F, // horizontal half line             (rw) 12 bits
     HSERR           = 0x10, // horizontal serration             (rw) 12 bits
     CNTTST          = 0x11, // Swatch counter test value        (rw) 12 bits
     SWATCH_CTRL     = 0x12, // Swatch timing generator control  (rw) 11 bits
     GBASE           = 0x13, // graphics base address            (rw) 22 bits, 32 byte aligned
     ROW_WORDS       = 0x14, // framebuffer pitch                (rw) 15 bits, 32 byte aligned
-    MON_SENSE       = 0x15, // Monitor sense control & status   (rw)  9 bits
+    MON_SENSE       = 0x15, // Monitor sense control & status   (rw)  9 bits (three groups of 3-bits; the two LSB groups are writable)
     MISC_ENABLES    = 0x16, // controls chip's features         (rw) 12 bits
     GSC_DIVIDE      = 0x17, // graphics clock divide count      (rw)  2 bits
     REFRESH_COUNT   = 0x18, // VRAM refresh counter             (rw) 10 bits
@@ -72,18 +72,33 @@ enum ControlRegs : int {
 
 // Bit definitions for the video timing generator (Swatch) control register.
 enum {
+//  1               = 1 <<  0, //
+//  1               = 1 <<  1, //
+    VSYNC_POLARITY  = 1 <<  2, // 0 - negative, 1 - positive
     RESET_TIMING    = 1 <<  3, // toggle this bit to change timing parameters
+//  1               = 1 <<  4, //
+//  1               = 1 <<  5, //
+    HSYNC_POLARITY  = 1 <<  6, // 0 - negative, 1 - positive
+//  0               = 1 <<  7, //
+    INTERLACED      = 1 <<  8, // 0 - progressive, 1 = interlaced
+//  0=unused        = 1 <<  9,
     DISABLE_TIMING  = 1 << 10, // 1 - disable video timing, 0 - enable it
 };
 
 // Bit definitions for MISC_ENABLES register.
 enum {
-    SCAN_CONTROL        = 1 <<  0, // 0 - interlaced, 1 - progressive
-    FB_ENDIAN_LITTLE    = 1 <<  1, // framebuffer endianness: 0 - big, 1 - little
-//  ?                   = 1 <<  4,
-//  ?                   = 1 <<  5,
-    VRAM_WIDE_MODE      = 1 <<  6, // VRAM bus width: 1 - 128bit, 0 - 64bit
-    BLANK_DISABLE       = 1 << 11, // 0 - enable blanking, 1 - disable it
+    SCAN_CONTROL          = 1 <<  0, // 0 - interlaced, 1 - progressive; opposite of INTERLACED above
+    FB_ENDIAN_LITTLE      = 1 <<  1, // framebuffer endianness: 0 - big, 1 - little // 1 also makes ControlRegs big endian
+    DOUBLE_BUFFERING      = 1 <<  2, // the same data transfers are generated for both the standard bank of VRAM and the optional bank
+    STANDARD_BANK_DISABLE = 1 <<  3, // 0 - data transfers are to be performed for the standard bank of VRAM
+    SHIFT_CLOCK           = 1 <<  4, // shift clock is to be generated
+    DETECT_PAGE_HITS      = 1 <<  5, // VRAM state machines detect page hits on the system bus to frame buffer single beat writes
+    VRAM_WIDE_MODE        = 1 <<  6, // VRAM bus width: 1 - 128bit, 0 - 64bit
+    MHZ_30_50             = 1 <<  7, // 0 - 50 MHz, 1 - 33 MHz // setting this to 33 MHz causes system to hang
+    VSYNC_DISABLE         = 1 <<  8, // 0 - enable vertical sync, 1 - disable it
+    HSYNC_DISABLE         = 1 <<  9, // 0 - enable horizontal sync, 1 - disable it
+    CSYNC_DISABLE         = 1 << 10, // 0 - enable composite sync, 1 - disable it
+    BLANK_DISABLE         = 1 << 11, // 0 - enable blanking, 1 - disable it
 };
 
 // Bit definitions for INT_ENABLE & INT_STATUS registers.
@@ -93,24 +108,6 @@ enum {
     VBL_IRQ_STAT = 1 << 2, // VBL interrupt status bit (INT_STATUS)
 };
 
-namespace RadacalRegs {
-
-enum RadacalRegs : uint8_t {
-    ADDRESS         = 0, // address register
-    CURSOR_CLUT     = 1, // cursor palette data
-    MULTI           = 2, // multipurpose section
-    CLUT_DATA       = 3, // color palette data
-
-    // multipurpose section registers
-    CURSOR_POS_HI   = 0x10, // cursor position, high-order byte
-    CURSOR_POS_LO   = 0x11, // cursor position, low-order byte
-    MISC_CTRL       = 0x20, // miscellaneus control bits
-    DBL_BUF_CTRL    = 0x21, // double buffer control bits
-    TEST_CTRL       = 0x22, // enable/disable DAC tests
-};
-
-}; // namespace RadacalRegs
-
 class ControlVideo : public PCIDevice, public VideoCtrlBase {
 public:
     ControlVideo();

machines/machinetnt.cpp

@@ -61,11 +61,11 @@ int initialize_tnt(std::string& id)
     // attach IOBus Device #1 0xF301A000
     gMachineObj->add_device("BoardReg1", std::unique_ptr<BoardRegister>(
         new BoardRegister("Board Register 1",
-            0x3F                                        | // pull up all PRSNT bits
-            ((GET_BIN_PROP("emmo") ^ 1) << 8)           | // factory tests (active low)
-            ((GET_BIN_PROP("has_sixty6") ^ 1) << 13)    | // composite video out (active low)
-            (GET_BIN_PROP("has_mesh") << 14)            | // fast SCSI (active high)
-            0x8000U                                       // pull up unused bits
+            0x3F                                                                       | // pull up all PRSNT bits
+            ((GET_BIN_PROP("emmo") ^ 1) << 8)                                          | // factory tests (active low)
+            ((gMachineObj->get_comp_by_name_optional("Sixty6Video") == nullptr) << 13) | // composite video out (active low)
+            ((gMachineObj->get_comp_by_name_optional("MeshTnt") != nullptr) << 14)     | // fast SCSI (active high)
+            0x8000U                                                                      // pull up unused bits
     )));
     gc_obj->attach_iodevice(0, dynamic_cast<BoardRegister*>(gMachineObj->get_comp_by_name("BoardReg1")));
 
@@ -131,10 +131,6 @@ static const PropMap pm7500_settings = {
         new IntProperty( 0, vector<uint32_t>({0, 4, 8, 16, 32, 64, 128}))},
     {"emmo",
         new BinProperty(0)},
-    {"has_sixty6",
-        new BinProperty(0)},
-    {"has_mesh",
-        new BinProperty(1)},
     {"cpu",
         new StrProperty(
             cpu == PPC_VER::MPC601  ? "601" :
@@ -144,9 +140,17 @@ static const PropMap pm7500_settings = {
 };
 
 static vector<string> pm7500_devices = {
+    "Hammerhead", "Bandit1", "Chaos", "ScsiMesh", "MeshTnt", "GrandCentral", "ControlVideo"
+};
+
+static vector<string> pm8500_devices = {
     "Hammerhead", "Bandit1", "Chaos", "ScsiMesh", "MeshTnt", "GrandCentral", "ControlVideo", "Sixty6Video"
 };
 
+static vector<string> pm9500_devices = {
+    "Hammerhead", "Bandit1", "Bandit2", "ScsiMesh", "MeshTnt", "GrandCentral"
+};
+
 static const MachineDescription pm7300_descriptor = {
     .name = "pm7300",
     .description = "Power Macintosh 7300",
@@ -163,5 +167,50 @@ static const MachineDescription pm7500_descriptor = {
     .init_func = &initialize_tnt
 };
 
+static const MachineDescription pm8500_descriptor = {
+    .name = "pm8500",
+    .description = "Power Macintosh 8500",
+    .devices = pm8500_devices,
+    .settings = pm7500_settings<PPC_VER::MPC604>,
+    .init_func = &initialize_tnt
+};
+
+static const MachineDescription pm9500_descriptor = {
+    .name = "pm9500",
+    .description = "Power Macintosh 9500",
+    .devices = pm9500_devices,
+    .settings = pm7500_settings<PPC_VER::MPC604>,
+    .init_func = &initialize_tnt
+};
+
+static const MachineDescription pm7600_descriptor = {
+    .name = "pm7600",
+    .description = "Power Macintosh 7600",
+    .devices = pm7500_devices,
+    .settings = pm7500_settings<PPC_VER::MPC604E>,
+    .init_func = &initialize_tnt
+};
+
+static const MachineDescription pm8600_descriptor = {
+    .name = "pm8600",
+    .description = "Power Macintosh 8600",
+    .devices = pm8500_devices,
+    .settings = pm7500_settings<PPC_VER::MPC604E>,
+    .init_func = &initialize_tnt
+};
+
+static const MachineDescription pm9600_descriptor = {
+    .name = "pm9600",
+    .description = "Power Macintosh 9600",
+    .devices = pm9500_devices,
+    .settings = pm7500_settings<PPC_VER::MPC604E>,
+    .init_func = &initialize_tnt
+};
+
 REGISTER_MACHINE(pm7300, pm7300_descriptor);
 REGISTER_MACHINE(pm7500, pm7500_descriptor);
+REGISTER_MACHINE(pm8500, pm8500_descriptor);
+REGISTER_MACHINE(pm9500, pm9500_descriptor);
+REGISTER_MACHINE(pm7600, pm7600_descriptor);
+REGISTER_MACHINE(pm8600, pm8600_descriptor);
+REGISTER_MACHINE(pm9600, pm9600_descriptor);