mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-06-02 05:41:39 +00:00
500 lines
16 KiB
C++
500 lines
16 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-20 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "displayid.h"
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#include "endianswap.h"
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#include "memaccess.h"
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#include "pcidevice.h"
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#include <atirage.h>
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#include <cstdint>
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#include <map>
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#include <thirdparty/loguru/loguru.hpp>
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/* Mach64 post dividers. */
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static const int mach64_post_div[8] = {
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1, 2, 4, 8, // standard post dividers
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3, 5, 6, 12 // alternate post dividers
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};
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/* Human readable Mach64 HW register names for easier debugging. */
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static const std::map<uint16_t, std::string> mach64_reg_names = {
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{0x0000, "CRTC_H_TOTAL_DISP"},
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{0x0004, "CRTC_H_SYNC_STRT_WID"},
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{0x0008, "CRTC_V_TOTAL_DISP"},
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{0x000C, "CRTC_V_SYNC_STRT_WID"},
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{0x0010, "CRTC_VLINE_CRNT_VLINE"},
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{0x0014, "CRTC_OFF_PITCH"},
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{0x0018, "CRTC_INT_CNTL"},
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{0x001C, "CRTC_GEN_CNTL"},
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{0x0020, "DSP_CONFIG"},
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{0x0024, "DSP_ON_OFF"},
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{0x002C, "MEM_BUF_CNTL"},
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{0x0034, "MEM_ADDR_CFG"},
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{0x0040, "OVR_CLR"},
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{0x0044, "OVR_WID_LEFT_RIGHT"},
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{0x0048, "OVR_WID_TOP_BOTTOM"},
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{0x0060, "CUR_CLR0"},
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{0x0064, "CUR_CLR1"},
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{0x0068, "CUR_OFFSET"},
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{0x006C, "CUR_HORZ_VERT_POSN"},
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{0x0078, "GP_IO"},
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{0x007C, "HW_DEBUG"},
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{0x0080, "SCRATCH_REG0"},
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{0x0084, "SCRATCH_REG1"},
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{0x0088, "SCRATCH_REG2"},
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{0x008C, "SCRATCH_REG3"},
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{0x0090, "CLOCK_CNTL"},
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{0x00A0, "BUS_CNTL"},
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{0x00AC, "EXT_MEM_CNTL"},
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{0x00B0, "MEM_CNTL"},
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{0x00C0, "DAC_REGS"},
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{0x00C4, "DAC_CNTL"},
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{0x00D0, "GEN_TEST_CNTL"},
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{0x00D4, "CUSTOM_MACRO_CNTL"},
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{0x00E0, "CONFIG_CHIP_ID"},
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{0x00E4, "CONFIG_STAT0"},
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{0x01B4, "SRC_CNTL"},
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{0x01FC, "SCALE_3D_CNTL"},
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{0x0310, "FIFO_STAT"},
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{0x0338, "GUI_STAT"},
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};
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ATIRage::ATIRage(uint16_t dev_id, uint32_t mem_amount) : PCIDevice("ati-rage") {
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uint8_t asic_id;
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this->vram_size = mem_amount << 20;
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/* allocate video RAM */
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this->vram_ptr = new uint8_t[this->vram_size];
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/* ATI Rage driver needs to know ASIC ID (manufacturer's internal chip code)
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to operate properly */
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switch (dev_id) {
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case ATI_RAGE_PRO_DEV_ID:
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asic_id = 0x5C; // R3B/D/P-A4 fabricated by UMC
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break;
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default:
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asic_id = 0xDD;
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LOG_F(WARNING, "ATI Rage: bogus ASIC ID assigned!");
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}
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/* set up PCI configuration space header */
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WRITE_DWORD_LE_A(&this->pci_cfg[0], (dev_id << 16) | ATI_PCI_VENDOR_ID);
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WRITE_DWORD_LE_A(&this->pci_cfg[8], (0x030000 << 8) | asic_id);
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WRITE_DWORD_LE_A(&this->pci_cfg[0x3C], 0x00080100);
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/* stuff default values into chip registers */
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WRITE_DWORD_LE_A(&this->block_io_regs[ATI_CONFIG_CHIP_ID],
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(asic_id << 24) | dev_id);
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/* initialize display identification */
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this->disp_id = new DisplayID();
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}
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ATIRage::~ATIRage()
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{
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if (this->vram_ptr) {
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delete this->vram_ptr;
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}
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delete (this->disp_id);
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}
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const char* ATIRage::get_reg_name(uint32_t reg_offset) {
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auto iter = mach64_reg_names.find(reg_offset & ~3);
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if (iter != mach64_reg_names.end()) {
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return iter->second.c_str();
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} else {
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return "unknown Mach64 register";
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}
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}
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uint32_t ATIRage::read_reg(uint32_t offset, uint32_t size) {
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uint32_t res;
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switch (offset & ~3) {
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case ATI_GP_IO:
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break;
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case ATI_CLOCK_CNTL:
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/* reading from internal PLL registers */
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if (offset == ATI_CLOCK_CNTL+2 && size == 1 &&
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!(this->block_io_regs[ATI_CLOCK_CNTL+1] & 0x2)) {
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return this->plls[this->block_io_regs[ATI_CLOCK_CNTL+1] >> 2];
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}
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break;
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case ATI_DAC_REGS:
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if (offset == ATI_DAC_DATA) {
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this->block_io_regs[ATI_DAC_DATA] =
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this->palette[this->block_io_regs[ATI_DAC_R_INDEX]][this->comp_index];
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this->comp_index++; /* move to next color component */
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if (this->comp_index >= 3) {
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/* autoincrement reading index - move to next palette entry */
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(this->block_io_regs[ATI_DAC_R_INDEX])++;
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this->comp_index = 0;
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}
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}
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break;
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default:
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LOG_F(
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INFO,
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"ATI Rage: read I/O reg %s at 0x%X, size=%d, val=0x%X",
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get_reg_name(offset),
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offset,
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size,
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read_mem(&this->block_io_regs[offset], size));
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}
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if (offset > sizeof(this->block_io_regs)) {
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LOG_F(WARNING, "ATI Rage: register offset 0x%04X out of bounds!", offset);
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return 0;
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}
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res = read_mem(&this->block_io_regs[offset], size);
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return res;
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}
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void ATIRage::write_reg(uint32_t offset, uint32_t value, uint32_t size) {
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uint32_t gpio_val;
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uint16_t gpio_dir;
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if (offset > sizeof(this->block_io_regs)) {
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LOG_F(WARNING, "ATI Rage: register offset 0x%04X out of bounds!", offset);
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return;
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}
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/* size-dependent endian conversion */
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write_mem(&this->block_io_regs[offset], value, size);
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switch (offset & ~3) {
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case ATI_CRTC_GEN_CNTL:
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if (this->block_io_regs[ATI_CRTC_GEN_CNTL+3] & 2) {
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this->crtc_enable();
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} else {
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this->crtc_on = false;
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}
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break;
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case ATI_GP_IO:
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if (offset < (ATI_GP_IO + 2)) {
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gpio_val = READ_DWORD_LE_A(&this->block_io_regs[ATI_GP_IO]);
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gpio_dir = (gpio_val >> 16) & 0x3FFF;
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WRITE_WORD_LE_A(
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&this->block_io_regs[ATI_GP_IO],
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this->disp_id->read_monitor_sense(gpio_val, gpio_dir));
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}
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break;
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case ATI_CLOCK_CNTL:
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/* writing to internal PLL registers */
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if (offset == ATI_CLOCK_CNTL+2 && size == 1 &&
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(this->block_io_regs[ATI_CLOCK_CNTL+1] & 0x2)) {
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int pll_addr = this->block_io_regs[ATI_CLOCK_CNTL+1] >> 2;
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uint8_t pll_data = this->block_io_regs[ATI_CLOCK_CNTL+2];
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this->plls[pll_addr] = pll_data;
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LOG_F(INFO, "ATI Rage: PLL #%d set to 0x%02X", pll_addr, pll_data);
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} else if (offset == ATI_CLOCK_CNTL && size == 1) {
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LOG_F(INFO, "ATI Rage: CLOCK_SEL = 0x%02X",
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this->block_io_regs[ATI_CLOCK_CNTL] & 3);
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}
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break;
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case ATI_DAC_REGS:
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switch (offset) {
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/* writing to read/write index registers resets color component index */
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case ATI_DAC_W_INDEX:
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case ATI_DAC_R_INDEX:
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this->comp_index = 0;
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break;
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case ATI_DAC_DATA:
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this->palette[this->block_io_regs[ATI_DAC_W_INDEX]][this->comp_index] = value & 0xFF;
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this->comp_index++; /* move to next color component */
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if (this->comp_index >= 3) {
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LOG_F(
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INFO,
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"ATI DAC palette entry #%d set to R=%X, G=%X, B=%X",
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this->block_io_regs[ATI_DAC_W_INDEX],
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this->palette[this->block_io_regs[ATI_DAC_W_INDEX]][0],
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this->palette[this->block_io_regs[ATI_DAC_W_INDEX]][1],
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this->palette[this->block_io_regs[ATI_DAC_W_INDEX]][2]);
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/* autoincrement writing index - move to next palette entry */
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(this->block_io_regs[ATI_DAC_W_INDEX])++;
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this->comp_index = 0;
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}
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}
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break;
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default:
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LOG_F(
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INFO,
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"ATI Rage: %s register at 0x%X set to 0x%X",
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get_reg_name(offset),
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offset & ~3,
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READ_DWORD_LE_A(&this->block_io_regs[offset & ~3]));
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}
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}
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uint32_t ATIRage::pci_cfg_read(uint32_t reg_offs, uint32_t size) {
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uint32_t res = 0;
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LOG_F(INFO, "Reading ATI Rage config space, offset = 0x%X, size=%d", reg_offs, size);
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res = read_mem(&this->pci_cfg[reg_offs], size);
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LOG_F(INFO, "Return value: 0x%X", res);
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return res;
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}
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void ATIRage::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size) {
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LOG_F(
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INFO,
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"Writing into ATI Rage PCI config space, offset = 0x%X, val=0x%X size=%d",
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reg_offs,
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BYTESWAP_32(value),
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size);
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switch (reg_offs) {
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case 0x10: /* BAR 0 */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_LE_A(&this->pci_cfg[CFG_REG_BAR0], 0xFF000000UL);
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}
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else {
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this->aperture_base = BYTESWAP_32(value);
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LOG_F(INFO, "ATI Rage aperture address set to 0x%08X", this->aperture_base);
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR0], value);
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this->host_instance->pci_register_mmio_region(this->aperture_base,
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APERTURE_SIZE, this);
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}
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break;
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case 0x14: /* BAR 1: I/O space base, 256 bytes wide */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR1], 0xFFFFFF01UL);
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}
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else {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR1], value);
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}
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break;
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case 0x18: /* BAR 2 */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR2], 0xFFFFF000UL);
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}
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else {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR2], value);
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}
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break;
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case CFG_REG_BAR3: /* unimplemented */
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case CFG_REG_BAR4: /* unimplemented */
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case CFG_REG_BAR5: /* unimplemented */
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WRITE_DWORD_BE_A(&this->pci_cfg[reg_offs], 0);
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break;
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case CFG_EXP_BASE: /* no expansion ROM */
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if (value == 0x00F8FFFFUL) {
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// return 0 (not implemented) when attempting to size the expansion ROM
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WRITE_DWORD_BE_A(&this->pci_cfg[reg_offs], 0);
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} else {
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WRITE_DWORD_BE_A(&this->pci_cfg[reg_offs], value);
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}
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break;
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default:
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write_mem(&this->pci_cfg[reg_offs], value, size);
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}
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}
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bool ATIRage::io_access_allowed(uint32_t offset, uint32_t* p_io_base) {
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if (!(this->pci_cfg[CFG_REG_CMD] & 1)) {
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LOG_F(WARNING, "ATI I/O space disabled in the command reg");
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return false;
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}
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uint32_t io_base = READ_DWORD_LE_A(&this->pci_cfg[CFG_REG_BAR1]) & ~3;
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if (offset < io_base || offset > (io_base + 0x100)) {
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LOG_F(WARNING, "Rage: I/O out of range, base=0x%X, offset=0x%X", io_base, offset);
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return false;
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}
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*p_io_base = io_base;
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return true;
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}
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bool ATIRage::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res) {
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uint32_t io_base;
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if (!this->io_access_allowed(offset, &io_base)) {
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return false;
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}
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*res = this->read_reg(offset - io_base, size);
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return true;
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}
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bool ATIRage::pci_io_write(uint32_t offset, uint32_t value, uint32_t size) {
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uint32_t io_base;
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if (!this->io_access_allowed(offset, &io_base)) {
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return false;
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}
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this->write_reg(offset - io_base, value, size);
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return true;
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}
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uint32_t ATIRage::read(uint32_t reg_start, uint32_t offset, int size)
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{
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LOG_F(8, "Reading ATI Rage PCI memory: region=%X, offset=%X, size %d", reg_start, offset, size);
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if (reg_start < this->aperture_base || offset > APERTURE_SIZE) {
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LOG_F(WARNING, "ATI Rage: attempt to read outside the aperture!");
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return 0;
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}
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if (offset < this->vram_size) {
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/* read from little-endian VRAM region */
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return read_mem(this->vram_ptr + offset, size);
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}
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else if (offset >= MEMMAP_OFFSET) {
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/* read from memory-mapped registers */
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return this->read_reg(offset - MEMMAP_OFFSET, size);
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}
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else {
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LOG_F(WARNING, "ATI Rage: read attempt from unmapped aperture region at 0x%08X", offset);
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}
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return 0;
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}
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void ATIRage::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
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{
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LOG_F(8, "Writing reg=%X, offset=%X, value=%X, size %d", reg_start, offset, value, size);
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if (reg_start < this->aperture_base || offset > APERTURE_SIZE) {
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LOG_F(WARNING, "ATI Rage: attempt to write outside the aperture!");
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return;
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}
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if (offset < this->vram_size) {
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/* write to little-endian VRAM region */
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write_mem(this->vram_ptr + offset, value, size);
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} else if (offset >= MEMMAP_OFFSET) {
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/* write to memory-mapped registers */
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this->write_reg(offset - MEMMAP_OFFSET, value, size);
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}
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else {
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LOG_F(WARNING, "ATI Rage: write attempt to unmapped aperture region at 0x%08X", offset);
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}
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}
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float ATIRage::calc_pll_freq(int scale, int fb_div) {
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return (ATI_XTAL * scale * fb_div) / this->plls[PLL_REF_DIV];
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}
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void ATIRage::verbose_pixel_format(int crtc_index) {
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if (crtc_index) {
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LOG_F(ERROR, "CRTC2 not supported yet");
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return;
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}
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const char* what = "Pixel format:";
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switch (this->block_io_regs[ATI_CRTC_GEN_CNTL+1] & 7) {
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case 1:
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LOG_F(INFO, "%s 4 bpp with DAC palette", what);
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break;
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case 2:
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// check the undocumented DAC_DIRECT bit
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if (this->block_io_regs[ATI_DAC_CNTL+1] & 4) {
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LOG_F(INFO, "%s 8 bpp direct color (RGB322)", what);
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} else {
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LOG_F(INFO, "%s 8 bpp with DAC palette", what);
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}
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break;
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case 3:
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LOG_F(INFO, "%s 15 bpp direct color (RGB555)", what);
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break;
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case 4:
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LOG_F(INFO, "%s 16 bpp direct color (RGB565)", what);
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break;
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case 5:
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LOG_F(INFO, "%s 24 bpp direct color (RGB888)", what);
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break;
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case 6:
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LOG_F(INFO, "%s 32 bpp direct color (ARGB8888)", what);
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break;
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default:
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LOG_F(ERROR, "ATI Rage: CRTC pixel format %d not supported",
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this->block_io_regs[ATI_CRTC_GEN_CNTL+2] & 7);
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}
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}
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void ATIRage::crtc_enable() {
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/* active (visible) width is specified in characters (8 px) - 1 */
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this->active_width = (this->block_io_regs[ATI_CRTC_H_TOTAL_DISP+2] + 1) * 8;
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/* active (visible) height is specified in lines - 1 */
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this->active_height =
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(READ_WORD_LE_A(&this->block_io_regs[ATI_CRTC_V_TOTAL_DISP+2]) & 0x7FFUL) + 1;
|
|
|
|
if ((this->plls[PLL_VCLK_CNTL] & 3) == 3) {
|
|
/* look up which VPLL ouput is requested */
|
|
int clock_sel = this->block_io_regs[ATI_CLOCK_CNTL] & 3;
|
|
|
|
/* calculate VPLL output frequency */
|
|
float vpll_freq = calc_pll_freq(2, this->plls[VCLK0_FB_DIV + clock_sel]);
|
|
|
|
/* calculate post divider's index */
|
|
/* NOTE: post divider's index has been extended by an additional
|
|
bit in Rage Pro. This bit is resided in PLL_EXT_CNTL register.
|
|
*/
|
|
int post_div_idx = ((this->plls[PLL_EXT_CNTL] >> (clock_sel + 2)) & 4) |
|
|
((this->plls[VCLK_POST_DIV] >> (clock_sel * 2)) & 3);
|
|
|
|
/* pixel clock = source_freq / post_div */
|
|
this->pixel_clock = vpll_freq / mach64_post_div[post_div_idx];
|
|
|
|
/* calculate display refresh rate */
|
|
int hori_total =
|
|
((READ_WORD_LE_A(&this->block_io_regs[ATI_CRTC_H_TOTAL_DISP])
|
|
& 0x1FFUL) + 1) * 8;
|
|
|
|
int vert_total =
|
|
(READ_WORD_LE_A(&this->block_io_regs[ATI_CRTC_V_TOTAL_DISP]) & 0x7FFUL) + 1;
|
|
|
|
this->refresh_rate = pixel_clock / hori_total / vert_total;
|
|
|
|
LOG_F(INFO, "ATI Rage: primary CRT controller enabled:");
|
|
LOG_F(INFO, "Video mode: %s",
|
|
(this->block_io_regs[ATI_CRTC_GEN_CNTL+3] & 1) ? "extended" : "VGA");
|
|
LOG_F(INFO, "Video width: %d px", this->active_width);
|
|
LOG_F(INFO, "Video height: %d px", this->active_height);
|
|
verbose_pixel_format(0);
|
|
LOG_F(INFO, "VPLL frequency: %f MHz", vpll_freq * 1e-6);
|
|
LOG_F(INFO, "Pixel (dot) clock: %f MHz", this->pixel_clock * 1e-6);
|
|
LOG_F(INFO, "Refresh rate: %f Hz", this->refresh_rate);
|
|
} else {
|
|
LOG_F(WARNING, "ATI Rage: VLCK source != VPLL!");
|
|
}
|
|
|
|
this->crtc_on = true;
|
|
}
|