315 lines
11 KiB
C++
315 lines
11 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Handling of low-level PPC exceptions. */
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#include <loguru.hpp>
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#include "ppcemu.h"
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#include "ppcmmu.h"
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#include <setjmp.h>
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#include <stdexcept>
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#include <string>
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jmp_buf exc_env; /* Global exception environment. */
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void ppc_exception_handler(Except_Type exception_type, uint32_t srr1_bits) {
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#ifdef CPU_PROFILING
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exceptions_processed++;
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#endif
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switch (exception_type) {
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case Except_Type::EXC_SYSTEM_RESET:
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ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
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ppc_next_instruction_address = 0x0100;
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break;
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case Except_Type::EXC_MACHINE_CHECK:
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if (!(ppc_state.msr & MSR::ME)) {
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/* TODO: handle internal checkstop */
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}
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ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
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ppc_next_instruction_address = 0x0200;
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break;
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case Except_Type::EXC_DSI:
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ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
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ppc_next_instruction_address = 0x0300;
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break;
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case Except_Type::EXC_ISI:
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if (exec_flags) {
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ppc_state.spr[SPR::SRR0] = ppc_next_instruction_address;
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} else {
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ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFCUL;
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}
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ppc_next_instruction_address = 0x0400;
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break;
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case Except_Type::EXC_EXT_INT:
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if (exec_flags) {
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ppc_state.spr[SPR::SRR0] = ppc_next_instruction_address;
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} else {
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ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFCUL) + 4;
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}
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ppc_next_instruction_address = 0x0500;
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break;
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case Except_Type::EXC_ALIGNMENT:
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ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
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ppc_next_instruction_address = 0x0600;
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break;
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case Except_Type::EXC_PROGRAM:
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ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
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ppc_next_instruction_address = 0x0700;
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break;
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case Except_Type::EXC_NO_FPU:
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ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
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ppc_next_instruction_address = 0x0800;
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break;
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case Except_Type::EXC_DECR:
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if (exec_flags) {
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ppc_state.spr[SPR::SRR0] = ppc_next_instruction_address;
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} else {
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ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFCUL) + 4;
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}
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ppc_next_instruction_address = 0x0900;
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break;
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case Except_Type::EXC_SYSCALL:
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ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFC) + 4;
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ppc_next_instruction_address = 0x0C00;
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break;
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case Except_Type::EXC_TRACE:
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ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFC) + 4;
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ppc_next_instruction_address = 0x0D00;
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break;
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default:
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ABORT_F("Unknown exception occurred: %X\n", (unsigned)exception_type);
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break;
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}
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ppc_state.spr[SPR::SRR1] = (ppc_state.msr & 0x0000FF73) | srr1_bits;
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ppc_state.msr &= 0xFFFB1041;
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/* copy MSR[ILE] to MSR[LE] */
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ppc_state.msr = (ppc_state.msr & ~MSR::LE) | !!(ppc_state.msr & MSR::ILE);
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if (ppc_state.msr & MSR::IP) {
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ppc_next_instruction_address |= 0xFFF00000;
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}
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exec_flags = EXEF_EXCEPTION;
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// perform context synchronization for recoverable exceptions
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if (exception_type != Except_Type::EXC_MACHINE_CHECK &&
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exception_type != Except_Type::EXC_SYSTEM_RESET) {
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do_ctx_sync();
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}
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mmu_change_mode();
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if (exception_type != Except_Type::EXC_EXT_INT && exception_type != Except_Type::EXC_DECR) {
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longjmp(exc_env, 2); /* return to the main execution loop. */
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}
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}
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[[noreturn]] void dbg_exception_handler(Except_Type exception_type, uint32_t srr1_bits) {
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std::string exc_descriptor;
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switch (exception_type) {
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case Except_Type::EXC_SYSTEM_RESET:
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exc_descriptor = "System reset exception occurred";
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break;
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case Except_Type::EXC_MACHINE_CHECK:
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exc_descriptor = "Machine check exception occurred";
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break;
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case Except_Type::EXC_DSI:
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case Except_Type::EXC_ISI:
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if (ppc_state.spr[SPR::DSISR] & 0x40000000)
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exc_descriptor = "DSI/ISI exception: unmapped memory access";
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else if (ppc_state.spr[SPR::DSISR] & 0x08000000)
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exc_descriptor = "DSI/ISI exception: access protection violation";
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else {
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if (exception_type == Except_Type::EXC_DSI)
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exc_descriptor = "DSI exception";
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else
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exc_descriptor = "ISI exception";
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}
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break;
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case Except_Type::EXC_EXT_INT:
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exc_descriptor = "External interrupt exception occurred";
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break;
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case Except_Type::EXC_ALIGNMENT:
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exc_descriptor = "Alignment exception occurred";
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break;
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case Except_Type::EXC_PROGRAM:
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exc_descriptor = "Program exception occurred";
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break;
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case Except_Type::EXC_NO_FPU:
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exc_descriptor = "Floating-Point unavailable exception occurred";
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break;
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case Except_Type::EXC_DECR:
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exc_descriptor = "Decrementer exception occurred";
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break;
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case Except_Type::EXC_SYSCALL:
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exc_descriptor = "Syscall exception occurred";
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break;
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case Except_Type::EXC_TRACE:
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exc_descriptor = "Trace exception occurred";
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break;
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}
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throw std::invalid_argument(exc_descriptor);
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}
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void ppc_floating_point_exception() {
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LOG_F(ERROR, "Floating point exception at 0x%08x for instruction 0x%08x",
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ppc_state.pc, ppc_cur_instruction);
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// mmu_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::FPU_EXCEPTION);
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}
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void ppc_alignment_exception(uint32_t ea)
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{
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uint32_t dsisr;
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switch (ppc_cur_instruction & 0xfc000000) {
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case 0x80000000: // lwz
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case 0x90000000: // stw
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case 0xa0000000: // lhz
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case 0xa8000000: // lha
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case 0xb0000000: // sth
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case 0xb8000000: // lmw
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case 0xc0000000: // lfs
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case 0xc8000000: // lfd
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case 0xd0000000: // stfs
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case 0xd8000000: // stfd
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case 0x84000000: // lwzu
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case 0x94000000: // stwu
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case 0xa4000000: // lhzu
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case 0xac000000: // lhau
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case 0xb4000000: // sthu
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case 0xbc000000: // stmw
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case 0xc4000000: // lfsu
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case 0xcc000000: // lfdu
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case 0xd4000000: // stfsu
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case 0xdc000000: // stfdu
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indirect_with_immediate_index:
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dsisr = ((ppc_cur_instruction >> 12) & 0x00004000) // bit 17 — Set to bit 5 of the instruction.
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| ((ppc_cur_instruction >> 17) & 0x00003c00); // bits 18–21 - set to bits 1–4 of the instruction.
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break;
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case 0x7c000000:
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switch (ppc_cur_instruction & 0xfc0007ff) {
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case 0x7c000028: // lwarx (invalid form - bits 15-21 of DSISR are identical to those of lwz)
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case 0x7c0002aa: // lwax (64-bit only)
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case 0x7c00042a: // lswx
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case 0x7c0004aa: // lswi
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case 0x7c00052a: // stswx
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case 0x7c0005aa: // stswi
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case 0x7c0002ea: // lwaux (64 bit only)
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case 0x7c00012c: // stwcx
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case 0x7c00042c: // lwbrx
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case 0x7c00052c: // stwbrx
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case 0x7c00062c: // lhbrx
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case 0x7c00072c: // sthbrx
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case 0x7c00026c: // eciwx // MPC7451
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case 0x7c00036c: // ecowx // MPC7451
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case 0x7c00002e: // lwzx
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case 0x7c00012e: // stwx
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case 0x7c00022e: // lhzx
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case 0x7c0002ae: // lhax
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case 0x7c00032e: // sthx
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case 0x7c00042e: // lfsx
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case 0x7c0004ae: // lfdx
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case 0x7c00052e: // stfsx
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case 0x7c0005ae: // stfdx
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case 0x7c00006e: // lwzux
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case 0x7c00016e: // stwux
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case 0x7c00026e: // lhzux
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case 0x7c0002ee: // lhaux
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case 0x7c00036e: // sthux
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case 0x7c00046e: // lfsux
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case 0x7c0004ee: // lfdux
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case 0x7c00056e: // stfsux
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case 0x7c0005ee: // stfdux
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indirect_with_index:
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dsisr = ((ppc_cur_instruction << 14) & 0x00018000) // bits 15–16 - set to bits 29–30 of the instruction.
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| ((ppc_cur_instruction << 8) & 0x00004000) // bit 17 - set to bit 25 of the instruction.
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| ((ppc_cur_instruction << 3) & 0x00003c00); // bits 18–21 - set to bits 21–24 of the instruction.
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break;
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case 0x7c0007ec:
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if ((ppc_cur_instruction & 0xffe007ff) == 0x7c0007ec) // dcbz
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goto indirect_with_index;
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/* fallthrough */
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default:
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goto unexpected_instruction;
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}
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break;
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default:
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unexpected_instruction:
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dsisr = 0;
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LOG_F(ERROR, "Alignment exception from unexpected instruction 0x%08x",
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ppc_cur_instruction);
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}
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// bits 22–26 - Set to bits 6–10 (source or destination) of the instruction.
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// Undefined for dcbz.
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dsisr |= ((ppc_cur_instruction >> 16) & 0x000003e0);
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if ((ppc_cur_instruction & 0xfc000000) == 0xb8000000) { // lmw
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LOG_F(ERROR, "Alignment exception from instruction 0x%08x (lmw). "
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"What to set DSISR bits 27-31?", ppc_cur_instruction);
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// dsisr |= ((ppc_cur_instruction >> ?) & 0x0000001f); // bits 27–31
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}
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else if ((ppc_cur_instruction & 0xfc0007ff) == 0x7c0004aa) { // lswi
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LOG_F(ERROR, "Alignment exception from instruction 0x%08x (lswi). "
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"What to set DSISR bits 27-31?", ppc_cur_instruction);
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// dsisr |= ((ppc_cur_instruction >> ?) & 0x0000001f); // bits 27–31
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}
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else if ((ppc_cur_instruction & 0xfc0007ff) == 0x7c00042a) { // lswx
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LOG_F(ERROR, "Alignment exception from instruction 0x%08x (lswx). "
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"What to set DSISR bits 27-31?", ppc_cur_instruction);
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// dsisr |= ((ppc_cur_instruction >> ?) & 0x0000001f); // bits 27–31
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}
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else {
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// bits 27–31 - Set to bits 11–15 of the instruction (rA)
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dsisr |= ((ppc_cur_instruction >> 16) & 0x0000001f);
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}
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ppc_state.spr[SPR::DSISR] = dsisr;
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ppc_state.spr[SPR::DAR] = ea;
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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}
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