218 lines
6.3 KiB
C++
218 lines
6.3 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file BigMac Ethernet controller definitions. */
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#ifndef BIG_MAC_H
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#define BIG_MAC_H
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#include <devices/common/hwcomponent.h>
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#include <cinttypes>
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#include <memory>
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/* Ethernet cell IDs for various MacIO ASICs. */
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enum EthernetCellId : uint8_t {
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Heathrow = 0xB1,
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Paddington = 0xC7,
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};
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/* BigMac HW registers. */
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enum BigMacReg : uint16_t {
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XIFC = 0x000, // transceiver interface control
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TX_FIFO_CSR = 0x100,
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TX_FIFO_TH = 0x110,
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RX_FIFO_CSR = 0x120,
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CHIP_ID = 0x170,
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MIF_CSR = 0x180,
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GLOB_STAT = 0x200, // Apple: kSTAT, Sun: Global Status Register
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EVENT_MASK = 0x210, // ambiguously called INT_DISABLE in the Apple source
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SROM_CSR = 0x190,
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TX_SW_RST = 0x420,
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TX_CONFIG = 0x430,
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PEAK_ATT = 0x4E0, // Apple: kPAREG, Sun: PeakAttempts Register
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NC_CNT = 0x500, // Normal Collision Counter
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NT_CNT = 0x510, // Apple: Network Collision Counter
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EX_CNT = 0x520, // Excessive Collision Counter
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LT_CNT = 0x530, // Late Collision Counter
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RNG_SEED = 0x540,
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RX_SW_RST = 0x620,
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RX_CONFIG = 0x630,
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MAC_ADDR_2 = 0x660,
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MAC_ADDR_1 = 0x670,
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MAC_ADDR_0 = 0x680,
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RX_FRM_CNT = 0x690, // Receive Frame Counter
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RX_LE_CNT = 0x6A0, // Length Error Counter
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RX_AE_CNT = 0x6B0, // Alignment Error Counter
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RX_FE_CNT = 0x6C0, // FCS Error Counter
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RX_CVE_CNT = 0x6E0, // Code Violation Error Counter
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HASH_TAB_3 = 0x700,
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HASH_TAB_2 = 0x710,
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HASH_TAB_1 = 0x720,
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HASH_TAB_0 = 0x730,
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};
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/* MIF_CSR bit definitions. */
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enum {
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Mif_Clock = 1 << 0,
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Mif_Data_Out = 1 << 1,
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Mif_Data_Out_En = 1 << 2,
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Mif_Data_In = 1 << 3
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};
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/* SROM_CSR bit definitions. */
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enum {
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Srom_Chip_Select = 1 << 0,
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Srom_Clock = 1 << 1,
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Srom_Data_In = 1 << 2,
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Srom_Data_Out = 1 << 3,
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};
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/* Serial EEPROM states (see ST93C46 datasheet). */
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enum {
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Srom_Start,
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Srom_Opcode,
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Srom_Address,
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Srom_Read_Data,
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};
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/* MII frame states. */
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enum MII_FRAME_SM {
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Preamble,
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Start,
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Opcode,
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Phy_Address,
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Reg_Address,
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Turnaround,
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Read_Data,
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Write_Data,
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Stop
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};
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/* PHY control/status registers. */
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enum {
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PHY_BMCR = 0,
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PHY_BMSR = 1,
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PHY_ID1 = 2,
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PHY_ID2 = 3,
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PHY_ANAR = 4,
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};
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class BigMac : public HWComponent {
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public:
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BigMac(uint8_t id);
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~BigMac() = default;
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static std::unique_ptr<HWComponent> create_for_heathrow() {
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return std::unique_ptr<BigMac>(new BigMac(EthernetCellId::Heathrow));
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}
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static std::unique_ptr<HWComponent> create_for_paddington() {
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return std::unique_ptr<BigMac>(new BigMac(EthernetCellId::Paddington));
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}
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// BigMac register accessors
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uint16_t read(uint16_t reg_offset);
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void write(uint16_t reg_offset, uint16_t value);
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protected:
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void chip_reset();
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// MII methods
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bool mii_rcv_value(uint16_t& var, uint8_t num_bits, uint8_t next_bit);
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void mii_rcv_bit();
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void mii_xmit_bit(const uint8_t bit_val);
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void mii_reset();
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// PHY control/status methods
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void phy_reset();
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uint16_t phy_reg_read(uint8_t reg_num);
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void phy_reg_write(uint8_t reg_num, uint16_t value);
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// MAC Serial EEPROM methods
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void srom_reset();
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bool srom_rcv_value(uint16_t& var, uint8_t num_bits, uint8_t next_bit);
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void srom_xmit_bit(const uint8_t bit_val);
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private:
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uint8_t chip_id; // BigMac Chip ID
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// BigMac state
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uint16_t tx_reset = 0; // self-clearing one-bit register
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uint16_t tx_if_ctrl = 0;
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uint16_t rng_seed;
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uint16_t norm_coll_cnt = 0;
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uint16_t net_coll_cnt = 0;
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uint16_t excs_coll_cnt = 0;
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uint16_t late_coll_cnt = 0;
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uint16_t rcv_frame_cnt = 0;
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uint8_t len_err_cnt = 0;
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uint8_t align_err_cnt = 0;
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uint8_t fcs_err_cnt = 0;
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uint8_t cv_err_cnt = 0;
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uint8_t peak_attempts = 0;
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uint8_t tx_fifo_tresh = 0;
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bool tx_fifo_enable = false;
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bool rx_fifo_enable = false;
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uint16_t tx_fifo_size = 0;
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uint16_t rx_fifo_size = 0;
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uint16_t hash_table[4] = {};
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uint16_t mac_addr_flt[3] = {};
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uint16_t tx_config = 0;
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uint16_t rx_config = 0;
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// Interrupt state
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uint16_t event_mask = 0xFFFFU; // inverted mask: 0 - enabled, 1 - disabled
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uint16_t stat = 0;
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// MII state
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uint8_t mif_csr_old = 0;
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uint8_t mii_bit_counter = 0;
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uint16_t mii_start = 0;
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uint16_t mii_stop = 0;
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uint16_t mii_opcode = 0;
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uint16_t mii_phy_address = 0;
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uint16_t mii_reg_address = 0;
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uint16_t mii_turnaround = 0;
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uint16_t mii_data = 0;
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uint8_t mii_in_bit = 1;
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MII_FRAME_SM mii_state = MII_FRAME_SM::Preamble;
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// PHY state
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uint32_t phy_oui;
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uint8_t phy_model;
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uint8_t phy_rev;
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uint16_t phy_bmcr;
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uint16_t phy_anar;
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// MAC SROM state
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uint8_t srom_csr_old = 0;
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uint8_t srom_bit_counter = 0;
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uint16_t srom_opcode = 0;
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uint16_t srom_address = 0;
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uint8_t srom_in_bit = 0;
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uint8_t srom_state = Srom_Start;
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uint16_t srom_data[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0xDEAD, 0xBEEF, 0xBABE}; // bogus MAC!!!
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};
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#endif // BIG_MAC_H
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