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ad4515721b
The SCC DMA Receive control registers previously returned std::rand(), a workaround to unblock Mac OS 8.5/8.5.1 boot which polls these registers expecting specific bit patterns. This caused non-deterministic bimodal boot times (~10s vs ~18s) on Power Mac 6100 as the guest would sometimes enter a ~7s polling loop depending on the random value. Add AmicSerialRcvDma to properly track the control register and byte count state for both SCC receive channels. Writes now update the status byte using the same bit manipulation as the transmit DMA channels, and reads return the tracked state. Also wire up the RX byte count registers (SCC_RXA/B_Byte_Cnt_Hi/Lo) which were previously ignored on write.