196 lines
7.2 KiB
C++
196 lines
7.2 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Taos video controller definitions. */
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/**
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Kudos to Keith Kaisershot @ blitter.net for his precious technical help!
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*/
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#ifndef TAOS_VIDEO_H
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#define TAOS_VIDEO_H
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#include <devices/common/i2c/i2c.h>
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#include <devices/common/mmiodevice.h>
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#include <devices/video/videoctrl.h>
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#include <cinttypes>
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#include <memory>
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#define TAOS_IOREG_BASE 0xF0800000
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#define TAOS_VRAM_REGION_BASE 0xF0000000
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#define TAOS_CLUT_BASE 0xF1000000
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#define TAOS_CHIP_VERSION 0xA5000000
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/** Taos register definitions. */
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// The implemented bits always start with the most significant bit (bit 31).
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// Unimplemented bits return zeroes.
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enum {
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// framebuffer configuration and control
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FB_BASE = 0x00, // 0x00, frame buffer base address, 19 bits, 32 byte aligned
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ROW_WORDS = 0x01, // 0x04, frame buffer pitch 12 bits, 32 byte aligned
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COLOR_MODE = 0x02, // 0x08, color mode 1 bit (MSB)
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VIDEO_MODE = 0x03, // 0x0C, current video mode, 2 bits (MSB)
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VEFS = 0x04, // 0x10, vertical even field start, 12 bits
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VOFS = 0x05, // 0x14, vertical odd field start, 12 bits
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HSTART = 0x06, // 0x18, horizontal active start, 12 bits
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VCONV_END = 0x07, // 0x1C, vertical convolution end, 12 bits
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CRT_CTRL = 0x08, // 0x20, frame buffer control, 11 bits
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CRT_TEST = 0x09, // 0x24, enables test features, 18 bits
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// timing generator parameters
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HEQ = 0x0B, // 0x2C, horizontal equalization, 8 bits
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HBWAY = 0x0C, // 0x30, horizontal breezeway, 12 bits
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HAL = 0x0D, // 0x34, horizontal active line, 12 bits
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HSERR = 0x0E, // 0x38, horizontal serration, 12 bits
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HFP = 0x0F, // 0x3C, horizontal front porch, 12 bits
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HPIX = 0x10, // 0x40, horizontal pixel count, 12 bits
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HSP = 0x11, // 0x44, horizontal sync pulse, 12 bits
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HLFLN = 0x12, // 0x48, horizontal half line, 12 bits
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VBPEQ = 0x13, // 0x4C, vertical back porch with EQ, 12 bits
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VBP = 0x14, // 0x50, vertical back porch, 12 bits
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VAL = 0x15, // 0x54, vertical active line, 12 bits
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VFP = 0x16, // 0x58, vertical front porch, 12 bits
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VFPEQ = 0x17, // 0x5C, vertical front porch with EQ, 12 bits
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VSYNC = 0x18, // 0x60, vertical sync starting point, 12 bits
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VHLINE = 0x19, // 0x64, vertical half line, 12 bits
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// GPIO and interrupts
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GPIO_IN = 0x1A, // 0x68, reads GPIO pins, 8 bits
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GPIO_CONFIG = 0x1B, // 0x6C, configure GPIO pins, 8 bits
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GPIO_OUT = 0x1C, // 0x70, outputs to GPIO pins, 8 bits
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GPIO_INT_CTRL = 0x1D, // 0x74, controls GPIO interrupts, 8 bits
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INT_LEVELS = 0x1E, // 0x78, interrupt levels, 12 bits (read-only)
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INT_ENABLES = 0x1F, // 0x7C, enable/disable interrupts, 12 bits
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INT_CLEAR = 0x20, // 0x80, clear pending interrupts, 12 bits (write-only)
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TAOS_VERSION = 0x23, // 0x8C, chip version, 8 bits (read-only)
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INT_SET = 0x24, // 0x90, allow setting interrupts 12 bits (write-only)
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HEB = 0x25, // 0x94, horizontal early blank, 12 bits
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};
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/** Taos video modes (see VIDEO_MODE register above). */
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enum {
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Progressive_Scan = 0, // Progressive scan
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Interlace, // Interlaced scan, no convolution
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Interlace_Conv, // Interlaced scan, convolution, no scaling
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Interlace_Conv_Scale // Interlaced scan, convolution, and scaling
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};
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/** CRT_CTRL bit definitions. */
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enum {
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ENABLE_VIDEO_OUT = 24,
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};
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#define REG_TO_INDEX(reg) ((reg) - HEQ)
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/** Monitor ID definitions used internally by the Taos driver. */
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// Those values are obtained by reading GPIO 0...2 pins that are
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// directly connected to the three-position mechanical switch
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// on the backside of the console. All signals are active low.
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enum {
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MON_ID_PAL = 3, // GPIO_0 = "0", GPIO_1 = "1", GPIO_2 = "1"
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MON_ID_NTSC = 5, // GPIO_0 = "1", GPIO_1 = "0", GPIO_2 = "1"
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MON_ID_VGA = 6 // GPIO_0 = "1", GPIO_1 = "1", GPIO_2 = "0"
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};
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/** Broktree Bt856 digital video encoder. */
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class Bt856 : public I2CDevice, public HWComponent {
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public:
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Bt856(uint8_t dev_addr) {
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supports_types(HWCompType::I2C_DEV);
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this->my_addr = dev_addr;
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};
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~Bt856() = default;
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// I2CDevice methods
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void start_transaction() {
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this->pos = 0; // reset read/write position
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};
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bool send_subaddress(uint8_t sub_addr) {
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return true;
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};
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bool send_byte(uint8_t data) {
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switch (this->pos) {
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case 0:
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this->reg_num = data;
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this->pos++;
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break;
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case 1:
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LOG_F(INFO, "Bt856: reg 0x%X set to 0x%X", this->reg_num, data);
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break;
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default:
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LOG_F(WARNING, "Bt856: too much data received!");
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return false; // return NACK
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}
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return true;
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};
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bool receive_byte(uint8_t* p_data) {
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*p_data = 0x60; // return my device ID
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return true;
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};
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private:
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uint8_t my_addr = 0;
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uint8_t reg_num = 0;
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int pos = 0;
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};
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class TaosVideo : public VideoCtrlBase, public MMIODevice {
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public:
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TaosVideo();
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~TaosVideo() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<TaosVideo>(new TaosVideo());
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}
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// MMIODevice methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size) override;
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) override;
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private:
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void enable_display();
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void convert_frame_15bpp_indexed(uint8_t *dst_buf, int dst_pitch);
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std::unique_ptr<AthensClocks> clk_gen = nullptr;
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std::unique_ptr<Bt856> vid_enc = nullptr;
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uint8_t gpio_cfg = 0;
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uint8_t mon_id = MON_ID_NTSC;
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uint8_t vsync_active = 0;
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uint8_t video_mode = 0;
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uint8_t *vram_ptr = nullptr;
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uint32_t fb_base = 0;
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uint32_t row_words = 0;
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uint32_t color_mode = 0;
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uint32_t crt_ctrl = 0;
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uint32_t int_enables = 0;
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uint32_t swatch_regs[15] = {};
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};
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#endif // TAOS_VIDEO_H
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