mirror of
https://github.com/dingusdev/dingusppc.git
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00f917f52e
This method is used by both pci_io_read and pci_io_write to determine if ISA type I/O access is allowed. The SPARSE_IO_BASE I/O address is defined. This I/O range is not defined by an I/O BAR.
569 lines
17 KiB
C++
569 lines
17 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** ATI Mach64 GX emulation.
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It emulates an ATI88800GX controller with an IBM RGB514 style RAMDAC.
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Emulation is limited to a basic frame buffer for now.
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*/
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#include <core/bitops.h>
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#include <devices/deviceregistry.h>
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#include <devices/video/atimach64defs.h>
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#include <devices/video/atimach64gx.h>
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#include <devices/video/displayid.h>
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#include <devices/video/rgb514defs.h>
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#include <loguru.hpp>
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#include <memaccess.h>
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#include <string>
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/* Human readable Mach64 HW register names for easier debugging. */
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static const std::map<uint16_t, std::string> mach64_reg_names = {
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#define one_reg_name(x) {ATI_ ## x, #x}
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one_reg_name(CRTC_H_TOTAL_DISP),
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one_reg_name(CRTC_H_SYNC_STRT_WID),
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one_reg_name(CRTC_V_TOTAL_DISP),
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one_reg_name(CRTC_V_SYNC_STRT_WID),
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one_reg_name(CRTC_VLINE_CRNT_VLINE),
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one_reg_name(CRTC_OFF_PITCH),
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one_reg_name(CRTC_INT_CNTL),
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one_reg_name(CRTC_GEN_CNTL),
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one_reg_name(DSP_CONFIG),
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one_reg_name(DSP_ON_OFF),
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one_reg_name(MEM_BUF_CNTL),
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one_reg_name(MEM_ADDR_CFG),
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one_reg_name(OVR_CLR),
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one_reg_name(OVR_WID_LEFT_RIGHT),
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one_reg_name(OVR_WID_TOP_BOTTOM),
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one_reg_name(CUR_CLR0),
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one_reg_name(CUR_CLR1),
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one_reg_name(CUR_OFFSET),
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one_reg_name(CUR_HORZ_VERT_POSN),
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one_reg_name(CUR_HORZ_VERT_OFF),
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one_reg_name(GP_IO),
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one_reg_name(HW_DEBUG),
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one_reg_name(SCRATCH_REG0),
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one_reg_name(SCRATCH_REG1),
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one_reg_name(SCRATCH_REG2),
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one_reg_name(SCRATCH_REG3),
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one_reg_name(CLOCK_CNTL),
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one_reg_name(BUS_CNTL),
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one_reg_name(EXT_MEM_CNTL),
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one_reg_name(MEM_CNTL),
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one_reg_name(DAC_REGS),
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one_reg_name(DAC_CNTL),
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one_reg_name(GEN_TEST_CNTL),
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one_reg_name(CUSTOM_MACRO_CNTL),
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one_reg_name(CONFIG_CNTL),
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one_reg_name(CONFIG_CHIP_ID),
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one_reg_name(CONFIG_STAT0),
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one_reg_name(DST_OFF_PITCH),
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one_reg_name(DST_X),
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one_reg_name(DST_Y),
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one_reg_name(DST_WIDTH),
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one_reg_name(DST_HEIGHT),
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one_reg_name(SRC_CNTL),
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one_reg_name(SCALE_3D_CNTL),
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one_reg_name(PAT_REG0),
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one_reg_name(PAT_REG1),
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one_reg_name(SC_LEFT),
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one_reg_name(SC_RIGHT),
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one_reg_name(SC_TOP),
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one_reg_name(SC_BOTTOM),
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one_reg_name(DP_BKGD_CLR),
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one_reg_name(DP_FRGD_CLR), // also DP_FOG_CLR for GT
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one_reg_name(DP_WRITE_MSK),
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one_reg_name(DP_PIX_WIDTH),
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one_reg_name(DP_MIX),
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one_reg_name(DP_SRC),
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one_reg_name(CLR_CMP_CNTL),
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one_reg_name(FIFO_STAT),
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one_reg_name(GUI_TRAJ_CNTL),
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one_reg_name(GUI_STAT),
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one_reg_name(MPP_CONFIG),
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one_reg_name(MPP_STROBE_SEQ),
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one_reg_name(MPP_ADDR),
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one_reg_name(MPP_DATA),
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one_reg_name(TVO_CNTL),
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one_reg_name(SETUP_CNTL),
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#undef one_reg_name
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};
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static const std::map<uint16_t, std::string> rgb514_reg_names = {
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#define one_reg_name(x) {Rgb514::x, #x}
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one_reg_name(MISC_CLK_CNTL),
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one_reg_name(HOR_SYNC_POS),
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one_reg_name(PWR_MNMGMT),
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one_reg_name(PIX_FORMAT),
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one_reg_name(PLL_CTL_1),
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one_reg_name(F0_M0),
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one_reg_name(F1_N0),
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one_reg_name(MISC_CNTL_1),
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one_reg_name(MISC_CNTL_2),
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one_reg_name(VRAM_MASK_LO),
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one_reg_name(VRAM_MASK_HI),
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#undef one_reg_name
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};
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AtiMach64Gx::AtiMach64Gx()
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: PCIDevice("ati-mach64-gx"), VideoCtrlBase(1024, 768)
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{
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supports_types(HWCompType::MMIO_DEV | HWCompType::PCI_DEV);
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// set up PCI configuration space header
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this->vendor_id = PCI_VENDOR_ATI;
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this->device_id = ATI_MACH64_GX_DEV_ID;
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this->class_rev = (0x030000 << 8) | 0x03;
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for (int i = 0; i < this->aperture_count; i++) {
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this->bars_cfg[i] = (uint32_t)(-this->aperture_size[i] | this->aperture_flag[i]);
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}
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this->finish_config_bars();
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this->pci_notify_bar_change = [this](int bar_num) {
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this->notify_bar_change(bar_num);
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};
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// declare expansion ROM containing FCode and Mac OS drivers
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if (this->attach_exp_rom_image(std::string("113-32900-004_Apple_MACH64.bin"))) {
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ABORT_F("%s: could not load ROM - this device won't work properly!",
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this->name.c_str());
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}
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// initialize display identification
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this->disp_id = std::unique_ptr<DisplayID> (new DisplayID(0x07, 0x3A));
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// allocate video RAM
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this->vram_size = 2 << 20; // 2MB ; up to 6MB supported
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this->vram_ptr = std::unique_ptr<uint8_t[]> (new uint8_t[this->vram_size]);
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// set up RAMDAC identification
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this->regs[ATI_CONFIG_STAT0] = 1 << 9;
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}
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void AtiMach64Gx::change_one_bar(uint32_t &aperture, uint32_t aperture_size, uint32_t aperture_new, int bar_num) {
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if (aperture != aperture_new) {
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if (aperture)
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this->host_instance->pci_unregister_mmio_region(aperture, aperture_size, this);
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aperture = aperture_new;
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if (aperture)
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this->host_instance->pci_register_mmio_region(aperture, aperture_size, this);
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LOG_F(INFO, "%s: aperture[%d] set to 0x%08X", this->name.c_str(), bar_num, aperture);
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}
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}
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void AtiMach64Gx::notify_bar_change(int bar_num)
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{
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if (bar_num) // only BAR0 is supported
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return;
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{
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change_one_bar(this->aperture_base[bar_num], this->aperture_size[bar_num], this->bars[bar_num] & ~15, bar_num);
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// copy aperture address to CONFIG_CNTL:CFG_MEM_AP_LOC
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insert_bits<uint32_t>(this->config_cntl, this->aperture_base[0] >> 22, ATI_CFG_MEM_AP_LOC, ATI_CFG_MEM_AP_LOC_size);
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}
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}
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#if 0
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uint32_t AtiMach64Gx::pci_cfg_read(uint32_t reg_offs, AccessDetails &details)
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{
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if (reg_offs < 64) {
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return PCIDevice::pci_cfg_read(reg_offs, details);
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}
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switch (reg_offs) {
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default:
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LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER();
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}
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return 0;
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}
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void AtiMach64Gx::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details)
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{
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if (reg_offs < 64) {
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PCIDevice::pci_cfg_write(reg_offs, value, details);
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return;
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}
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switch (reg_offs) {
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default:
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LOG_WRITE_UNIMPLEMENTED_CONFIG_REGISTER();
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}
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}
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#endif
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// map I/O register index to MMIO register offset
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static const uint32_t io_idx_to_reg_offset[32] = {
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ATI_CRTC_H_TOTAL_DISP,
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ATI_CRTC_H_SYNC_STRT_WID,
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ATI_CRTC_V_TOTAL_DISP,
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ATI_CRTC_V_SYNC_STRT_WID,
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ATI_CRTC_VLINE_CRNT_VLINE,
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ATI_CRTC_OFF_PITCH,
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ATI_CRTC_INT_CNTL,
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ATI_CRTC_GEN_CNTL,
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ATI_OVR_CLR,
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ATI_OVR_WID_LEFT_RIGHT,
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ATI_OVR_WID_TOP_BOTTOM,
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ATI_CUR_CLR0,
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ATI_CUR_CLR1,
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ATI_CUR_OFFSET,
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ATI_CUR_HORZ_VERT_POSN,
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ATI_CUR_HORZ_VERT_OFF,
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ATI_SCRATCH_REG0,
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ATI_SCRATCH_REG1,
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ATI_CLOCK_CNTL,
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ATI_BUS_CNTL,
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ATI_MEM_CNTL,
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ATI_MEM_VGA_WP_SEL,
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ATI_MEM_VGA_RP_SEL,
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ATI_DAC_REGS,
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ATI_DAC_CNTL,
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ATI_GEN_TEST_CNTL,
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ATI_CONFIG_CNTL,
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ATI_CONFIG_CHIP_ID,
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ATI_CONFIG_STAT0,
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ATI_GX_CONFIG_STAT1,
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ATI_INVALID,
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ATI_CRTC_H_TOTAL_DISP,
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};
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enum {
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SPARSE_IO_BASE = 0x2EC
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};
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bool AtiMach64Gx::io_access_allowed(uint32_t offset) {
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if ((offset & 0xFFFF03FC) == SPARSE_IO_BASE) {
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if (this->command & 1) {
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return true;
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}
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LOG_F(WARNING, "ATI I/O space disabled in the command reg");
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}
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return false;
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}
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bool AtiMach64Gx::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res)
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{
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if (!this->io_access_allowed(offset)) {
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return false;
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}
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uint32_t result = 0;
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// convert ISA-style I/O address to MMIO register offset
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offset = io_idx_to_reg_offset[(offset >> 10) & 0x1F] * 4 + (offset & 3);
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// CONFIG_CNTL is accessible from I/O space only
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if ((offset >> 2) == ATI_CONFIG_CNTL) {
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result = read_mem(((uint8_t *)&this->config_cntl) + (offset & 3), size);
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} else {
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result = BYTESWAP_SIZED(this->read_reg(offset, size), size);
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}
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*res = result;
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return true;
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}
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bool AtiMach64Gx::pci_io_write(uint32_t offset, uint32_t value, uint32_t size)
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{
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if (!this->io_access_allowed(offset)) {
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return false;
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}
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// convert ISA-style I/O address to MMIO register offset
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offset = io_idx_to_reg_offset[(offset >> 10) & 0x1F] * 4 + (offset & 3);
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// CONFIG_CNTL is accessible from I/O space only
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if ((offset >> 2) == ATI_CONFIG_CNTL) {
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write_mem(((uint8_t *)&this->config_cntl) + (offset & 3), value, size);
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switch (this->config_cntl & 3) {
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case 0:
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LOG_F(WARNING, "%s: linear aperture disabled!", this->name.c_str());
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break;
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case 1:
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LOG_F(INFO, "%s: aperture size set to 4MB", this->name.c_str());
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this->mm_regs_offset = MM_REGS_2_OFF;
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break;
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case 2:
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LOG_F(INFO, "%s: aperture size set to 8MB", this->name.c_str());
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this->mm_regs_offset = MM_REGS_0_OFF;
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break;
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default:
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LOG_F(ERROR, "%s: invalid aperture size in CONFIG_CNTL", this->name.c_str());
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}
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} else {
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this->write_reg(offset, BYTESWAP_SIZED(value, size), size);
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}
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return true;
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}
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const char* AtiMach64Gx::get_reg_name(uint32_t reg_num) {
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auto iter = mach64_reg_names.find(reg_num);
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if (iter != mach64_reg_names.end()) {
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return iter->second.c_str();
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} else {
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return "unknown Mach64 register";
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}
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}
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uint32_t AtiMach64Gx::read_reg(uint32_t reg_offset, uint32_t size)
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{
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uint32_t offset = reg_offset & 3;
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uint64_t result = this->regs[reg_offset >> 2];
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if (!offset && size == 4) { // fast path
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return static_cast<uint32_t>(result);
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} else { // slow path
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if ((offset + size) > 4) {
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result |= (uint64_t)(this->regs[(reg_offset >> 2) + 1]) << 32;
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}
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return static_cast<uint32_t>(extract_bits<uint64_t>(result, offset * 8, size * 8));
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}
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}
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void AtiMach64Gx::write_reg(uint32_t reg_offset, uint32_t value, uint32_t size)
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{
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uint8_t gpio_dirs, gpio_levels;
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int crtc_en;
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uint32_t offset = reg_offset & 3;
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reg_offset >>= 2;
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if (offset || size != 4) { // slow path
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if ((offset + size) > 4) {
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ABORT_F("%s: unaligned DWORD writes not implemented", this->name.c_str());
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}
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uint64_t old_val = this->regs[reg_offset];
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insert_bits<uint64_t>(old_val, value, offset * 8, size * 8);
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value = static_cast<uint32_t>(old_val);
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}
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switch (reg_offset) {
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case ATI_CRTC_OFF_PITCH:
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this->fb_pitch = extract_bits<uint32_t>(value, 22, 10) * 8;
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this->fb_ptr = &this->vram_ptr[extract_bits<uint32_t>(value, 0, 20) * 8];
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break;
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case ATI_CRTC_GEN_CNTL:
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if (bit_changed(this->regs[reg_offset], value, 6)) {
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if (value & 0x40) {
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this->blank_on = true;
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this->blank_display();
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} else {
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this->blank_on = false;
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}
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}
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if (bit_changed(this->regs[reg_offset], value, 25)) {
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if (!bit_set(value, 25)) {
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this->disable_crtc_internal();
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} else {
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this->blank_on = false;
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}
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}
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break;
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case ATI_DAC_REGS:
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if (size == 1) { // only byte accesses are allowed for DAC registers
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int dac_reg_addr = ((this->regs[ATI_DAC_CNTL] & 1) << 2) | offset;
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rgb514_write_reg(dac_reg_addr, extract_bits<uint32_t>(value, offset * 8, 8));
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}
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break;
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case ATI_DAC_CNTL:
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// monitor ID is usually accessed using 8bit writes
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if (offset == 3) {
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gpio_dirs = extract_bits<uint32_t>(value, 27, 3);
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gpio_levels = extract_bits<uint32_t>(value, 24, 3);
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gpio_levels = this->disp_id->read_monitor_sense(gpio_levels, gpio_dirs);
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insert_bits<uint32_t>(value, gpio_levels, 24, 3);
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}
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break;
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case ATI_CONFIG_STAT0:
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return; // prevent writes to this read-only register
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}
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this->regs[reg_offset] = value;
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}
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uint32_t AtiMach64Gx::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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if (rgn_start == this->aperture_base[0]) {
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if (offset < this->vram_size) {
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return read_mem(&this->vram_ptr[offset], size);
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}
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if (offset >= this->mm_regs_offset) {
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return BYTESWAP_SIZED(read_reg(offset - this->mm_regs_offset, size), size);
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}
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return 0;
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}
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// memory mapped expansion ROM region
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if (rgn_start == this->exp_rom_addr) {
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if (offset < this->exp_rom_size)
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return read_mem(&this->exp_rom_data[offset], size);
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return 0;
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}
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return 0;
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}
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void AtiMach64Gx::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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if (rgn_start == this->aperture_base[0]) {
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if (offset < this->vram_size) {
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return write_mem(&this->vram_ptr[offset], value, size);
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}
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if (offset >= this->mm_regs_offset) {
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return write_reg(offset - this->mm_regs_offset, BYTESWAP_SIZED(value, size), size);
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}
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return;
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}
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}
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void AtiMach64Gx::enable_crtc_internal()
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{
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uint32_t new_width, new_height;
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// check for unsupported modes and fail early
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if (!bit_set(this->regs[ATI_CRTC_GEN_CNTL], 24))
|
|
ABORT_F("%s: VGA not supported", this->name.c_str());
|
|
|
|
new_width = (extract_bits<uint32_t>(this->regs[ATI_CRTC_H_TOTAL_DISP], 16, 8) + 1) * 8;
|
|
new_height = extract_bits<uint32_t>(this->regs[ATI_CRTC_V_TOTAL_DISP], 16, 11) + 1;
|
|
|
|
if (new_width != this->active_width || new_height != this->active_height) {
|
|
this->create_display_window(new_width, new_height);
|
|
}
|
|
|
|
// calculate display refresh rate
|
|
this->hori_total = (extract_bits<uint32_t>(this->regs[ATI_CRTC_H_TOTAL_DISP], 0, 9) + 1) * 8;
|
|
this->vert_total = extract_bits<uint32_t>(this->regs[ATI_CRTC_V_TOTAL_DISP], 0, 11) + 1;
|
|
|
|
this->refresh_rate = this->pixel_clock / this->hori_total / this->vert_total;
|
|
|
|
// specify framebuffer converter
|
|
switch (this->pixel_depth) {
|
|
case 8:
|
|
this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
|
|
this->convert_frame_8bpp_indexed(dst_buf, dst_pitch);
|
|
};
|
|
break;
|
|
default:
|
|
ABORT_F("%s: unsupported pixel depth %d", this->name.c_str(), this->pixel_depth);
|
|
}
|
|
|
|
this->stop_refresh_task();
|
|
this->start_refresh_task();
|
|
|
|
this->crtc_on = true;
|
|
|
|
this->crtc_enable = 1;
|
|
}
|
|
|
|
void AtiMach64Gx::disable_crtc_internal()
|
|
{
|
|
this->blank_on = true;
|
|
this->blank_display();
|
|
this->crtc_enable = 0;
|
|
}
|
|
|
|
// ========================== IBM RGB514 related code ==========================
|
|
void AtiMach64Gx::rgb514_write_reg(uint8_t reg_addr, uint8_t value)
|
|
{
|
|
switch (reg_addr) {
|
|
case Rgb514::CLUT_ADDR_WR:
|
|
this->clut_index = value;
|
|
break;
|
|
case Rgb514::CLUT_DATA:
|
|
this->clut_color[this->comp_index++] = value;
|
|
if (this->comp_index >= 3) {
|
|
this->set_palette_color(this->clut_index, clut_color[0],
|
|
clut_color[1], clut_color[2], 0xFF);
|
|
this->clut_index++;
|
|
this->comp_index = 0;
|
|
}
|
|
break;
|
|
case Rgb514::CLUT_MASK:
|
|
if (value != 0xFF) {
|
|
LOG_F(WARNING, "RGB514: pixel mask set to 0x%X", value);
|
|
}
|
|
break;
|
|
case Rgb514::INDEX_LOW:
|
|
this->dac_idx_lo = value;
|
|
break;
|
|
case Rgb514::INDEX_HIGH:
|
|
this->dac_idx_hi = value;
|
|
break;
|
|
case Rgb514::INDEX_DATA:
|
|
this->rgb514_write_ind_reg((this->dac_idx_hi << 8) + this->dac_idx_lo, value);
|
|
break;
|
|
default:
|
|
ABORT_F("RGB514: access to unimplemented register at 0x%X", reg_addr);
|
|
}
|
|
}
|
|
|
|
const char* AtiMach64Gx::rgb514_get_reg_name(uint32_t reg_addr)
|
|
{
|
|
auto iter = rgb514_reg_names.find(reg_addr);
|
|
if (iter != rgb514_reg_names.end()) {
|
|
return iter->second.c_str();
|
|
} else {
|
|
return "unknown rgb514 register";
|
|
}
|
|
}
|
|
|
|
void AtiMach64Gx::rgb514_write_ind_reg(uint8_t reg_addr, uint8_t value)
|
|
{
|
|
this->dac_regs[reg_addr] = value;
|
|
|
|
switch (reg_addr) {
|
|
case Rgb514::MISC_CLK_CNTL:
|
|
if (value & PLL_ENAB) {
|
|
if ((this->dac_regs[Rgb514::PLL_CTL_1] & 3) != 1)
|
|
ABORT_F("RGB514: unsupported PLL source");
|
|
|
|
int m = 8 >> (this->dac_regs[Rgb514::F0_M0] >> 6);
|
|
int vco_div = (this->dac_regs[Rgb514::F0_M0] & 0x3F) + 65;
|
|
int ref_div = (this->dac_regs[Rgb514::F1_N0] & 0x1F) * m;
|
|
this->pixel_clock = ATI_XTAL * vco_div / ref_div;
|
|
LOG_F(INFO, "RGB514: dot clock set to %f Hz", this->pixel_clock);
|
|
}
|
|
break;
|
|
case Rgb514::PIX_FORMAT:
|
|
if (value == 3) {
|
|
this->pixel_depth = 8;
|
|
// HACK: not the best place for enabling display output!
|
|
this->enable_crtc_internal();
|
|
} else {
|
|
ABORT_F("RGB514: unimplemented pixel format %d", value);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const DeviceDescription AtiMach64Gx_Descriptor = {
|
|
AtiMach64Gx::create, {}, {}
|
|
};
|
|
|
|
REGISTER_DEVICE(AtiMach64Gx, AtiMach64Gx_Descriptor);
|