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This method is used by both pci_io_read and pci_io_write to determine if ISA type I/O access is allowed. The SPARSE_IO_BASE I/O address is defined. This I/O range is not defined by an I/O BAR.
99 lines
3.0 KiB
C++
99 lines
3.0 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** ATI Mach64 GX definitions. */
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#ifndef ATI_MACH64_GX_H
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#define ATI_MACH64_GX_H
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#include <devices/common/pci/pcidevice.h>
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#include <devices/video/displayid.h>
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#include <devices/video/videoctrl.h>
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#include <cinttypes>
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#include <memory>
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class AtiMach64Gx : public PCIDevice, public VideoCtrlBase {
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public:
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AtiMach64Gx();
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~AtiMach64Gx() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<AtiMach64Gx>(new AtiMach64Gx());
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}
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// PCI device methods
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bool supports_io_space(void) {
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return true;
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};
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// I/O space access methods
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bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res);
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bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size);
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// MMIODevice methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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protected:
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void notify_bar_change(int bar_num);
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const char* get_reg_name(uint32_t reg_offset);
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const char* rgb514_get_reg_name(uint32_t reg_offset);
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bool io_access_allowed(uint32_t offset);
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uint32_t read_reg(uint32_t reg_offset, uint32_t size);
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void write_reg(uint32_t reg_offset, uint32_t value, uint32_t size);
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void enable_crtc_internal();
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void disable_crtc_internal();
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void rgb514_write_reg(uint8_t reg_addr, uint8_t value);
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void rgb514_write_ind_reg(uint8_t reg_addr, uint8_t value);
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private:
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void change_one_bar(uint32_t &aperture, uint32_t aperture_size, uint32_t aperture_new, int bar_num);
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uint32_t regs[256] = {}; // internal registers
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int vram_size;
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// main aperture (16MB)
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const uint32_t aperture_count = 1;
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const uint32_t aperture_size[1] = { 0x1000000 };
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const uint32_t aperture_flag[1] = { 0 };
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uint32_t aperture_base[1] = { 0 };
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uint32_t config_cntl;
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uint32_t mm_regs_offset;
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int crtc_enable = 0;
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// RGB514 RAMDAC state
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uint8_t dac_idx_lo;
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uint8_t dac_idx_hi;
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uint8_t clut_index;
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uint8_t comp_index;
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uint8_t clut_color[3];
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uint8_t dac_regs[256];
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std::unique_ptr<DisplayID> disp_id;
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std::unique_ptr<uint8_t[]> vram_ptr;
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};
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#endif // ATI_MACH64_GX_H
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