mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-12-24 12:30:05 +00:00
f61854a0ae
PCIDevice - supports_io_space method now uses a flag has_io_space which is automatically set for PCI bridges or PCI devices that have an I/O BAR. atirage - Devices that have I/O BARs don't need a supports_io_space method. mpc106 - Devices that don't have I/O methods don't need a supports_io_space method.
100 lines
3.3 KiB
C++
100 lines
3.3 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef ATI_RAGE_H
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#define ATI_RAGE_H
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#include <devices/common/pci/pcidevice.h>
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#include <devices/video/atimach64defs.h>
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#include <devices/video/displayid.h>
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#include <devices/video/videoctrl.h>
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#include <cinttypes>
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#include <memory>
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/* Mach64 PLL register indices. */
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enum {
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PLL_REF_DIV = 2, // reference divider, same for all Mach64 clocks
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PLL_VCLK_CNTL = 5,
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VCLK_POST_DIV = 6,
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VCLK0_FB_DIV = 7, // feedback divider for VCLK0
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VCLK1_FB_DIV = 8, // feedback divider for VCLK1
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VCLK2_FB_DIV = 9, // feedback divider for VCLK2
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VCLK3_FB_DIV = 10, // feedback divider for VCLK3
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PLL_EXT_CNTL = 11,
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};
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class ATIRage : public PCIDevice, public VideoCtrlBase {
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public:
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ATIRage(uint16_t dev_id);
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~ATIRage() = default;
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static std::unique_ptr<HWComponent> create_gt() {
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return std::unique_ptr<ATIRage>(new ATIRage(ATI_RAGE_GT_DEV_ID));
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}
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static std::unique_ptr<HWComponent> create_pro() {
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return std::unique_ptr<ATIRage>(new ATIRage(ATI_RAGE_PRO_DEV_ID));
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}
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/* MMIODevice methods */
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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/* PCI device methods */
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uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details);
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details);
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/* I/O space access methods */
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bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res);
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bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size);
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protected:
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void notify_bar_change(int bar_num);
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const char* get_reg_name(uint32_t reg_offset);
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bool io_access_allowed(uint32_t offset);
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uint32_t read_reg(uint32_t offset, uint32_t size);
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void write_reg(uint32_t offset, uint32_t value, uint32_t size);
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float calc_pll_freq(int scale, int fb_div);
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void verbose_pixel_format(int crtc_index);
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void crtc_enable();
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void draw_hw_cursor(uint8_t *dst_buf, int dst_pitch);
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private:
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uint8_t mm_regs[2048] = {0}; // internal registers
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uint8_t plls[64] = {0}; // internal PLL registers
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/* Video RAM variables */
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std::unique_ptr<uint8_t[]> vram_ptr;
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uint32_t vram_size;
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uint32_t aperture_base = 0;
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uint32_t io_base = 0;
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uint8_t user_cfg = 8;
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std::unique_ptr<DisplayID> disp_id;
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int comp_index; /* color component index for DAC palette access */
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};
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#endif /* ATI_RAGE_H */
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