302 lines
8.0 KiB
C++
302 lines
8.0 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-20 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "displayid.h"
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#include "endianswap.h"
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#include "memreadwrite.h"
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#include "pcidevice.h"
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#include <atirage.h>
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#include <cstdint>
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#include <thirdparty/loguru/loguru.hpp>
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ATIRage::ATIRage(uint16_t dev_id) : PCIDevice("ati-rage") {
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WRITE_DWORD_BE_A(&this->pci_cfg[0], (dev_id << 16) | ATI_PCI_VENDOR_ID);
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WRITE_DWORD_BE_A(&this->pci_cfg[8], 0x0300005C);
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WRITE_DWORD_BE_A(&this->pci_cfg[0x3C], 0x00080100);
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this->disp_id = new DisplayID();
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}
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ATIRage::~ATIRage() {
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delete (this->disp_id);
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}
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uint32_t ATIRage::size_dep_read(uint8_t* buf, uint32_t size) {
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switch (size) {
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case 4:
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return READ_DWORD_LE_A(buf);
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break;
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case 2:
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return READ_WORD_LE_A(buf);
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break;
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case 1:
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return *buf;
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break;
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default:
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LOG_F(WARNING, "ATI Rage read: invalid size %d", size);
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return 0;
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}
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}
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void ATIRage::size_dep_write(uint8_t* buf, uint32_t value, uint32_t size) {
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switch (size) {
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case 4:
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WRITE_DWORD_BE_A(buf, value);
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break;
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case 2:
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WRITE_WORD_BE_A(buf, value & 0xFFFFU);
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break;
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case 1:
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*buf = value & 0xFF;
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}
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}
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const char* ATIRage::get_reg_name(uint32_t reg_offset) {
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const char* reg_name;
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switch (reg_offset & ~3) {
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case ATI_CRTC_H_TOTAL_DISP:
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reg_name = "CRTC_H_TOTAL_DISP";
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break;
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case ATI_CRTC_H_SYNC_STRT_WID:
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reg_name = "CRTC_H_SYNC_STRT_WID";
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break;
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case ATI_CRTC_V_TOTAL_DISP:
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reg_name = "CRTC_V_TOTAL_DISP";
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break;
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case ATI_CRTC_V_SYNC_STRT_WID:
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reg_name = "CRTC_V_SYNC_STRT_WID";
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break;
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case ATI_CRTC_OFF_PITCH:
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reg_name = "CRTC_OFF_PITCH";
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break;
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case ATI_CRTC_INT_CNTL:
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reg_name = "CRTC_INT_CNTL";
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break;
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case ATI_CRTC_GEN_CNTL:
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reg_name = "CRTC_GEN_CNTL";
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break;
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case ATI_DSP_CONFIG:
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reg_name = "DSP_CONFIG";
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break;
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case ATI_DSP_ON_OFF:
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reg_name = "DSP_ON_OFF";
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break;
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case ATI_MEM_ADDR_CFG:
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reg_name = "MEM_ADDR_CFG";
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break;
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case ATI_OVR_CLR:
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reg_name = "OVR_CLR";
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break;
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case ATI_OVR_WID_LEFT_RIGHT:
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reg_name = "OVR_WID_LEFT_RIGHT";
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break;
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case ATI_OVR_WID_TOP_BOTTOM:
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reg_name = "OVR_WID_TOP_BOTTOM";
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break;
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case ATI_GP_IO:
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reg_name = "GP_IO";
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break;
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case ATI_CLOCK_CNTL:
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reg_name = "CLOCK_CNTL";
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break;
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case ATI_BUS_CNTL:
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reg_name = "BUS_CNTL";
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break;
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case ATI_EXT_MEM_CNTL:
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reg_name = "EXT_MEM_CNTL";
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break;
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case ATI_MEM_CNTL:
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reg_name = "MEM_CNTL";
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break;
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case ATI_DAC_CNTL:
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reg_name = "DAC_CNTL";
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break;
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case ATI_GEN_TEST_CNTL:
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reg_name = "GEN_TEST_CNTL";
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break;
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case ATI_CFG_CHIP_ID:
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reg_name = "CONFIG_CHIP_ID";
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break;
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case ATI_CFG_STAT0:
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reg_name = "CONFIG_STAT0";
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break;
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default:
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reg_name = "unknown";
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}
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return reg_name;
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}
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uint32_t ATIRage::read_reg(uint32_t offset, uint32_t size) {
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uint32_t res;
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switch (offset & ~3) {
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case ATI_GP_IO:
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break;
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default:
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LOG_F(
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INFO,
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"ATI Rage: read I/O reg %s at 0x%X, size=%d, val=0x%X",
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get_reg_name(offset),
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offset,
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size,
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size_dep_read(&this->block_io_regs[offset], size));
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}
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res = size_dep_read(&this->block_io_regs[offset], size);
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return res;
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}
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void ATIRage::write_reg(uint32_t offset, uint32_t value, uint32_t size) {
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uint32_t gpio_val;
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uint16_t gpio_dir;
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/* size-dependent endian conversion */
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size_dep_write(&this->block_io_regs[offset], value, size);
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switch (offset & ~3) {
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case ATI_GP_IO:
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if (offset < (ATI_GP_IO + 2)) {
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gpio_val = READ_DWORD_LE_A(&this->block_io_regs[ATI_GP_IO]);
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gpio_dir = (gpio_val >> 16) & 0x3FFF;
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WRITE_WORD_LE_A(
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&this->block_io_regs[ATI_GP_IO],
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this->disp_id->read_monitor_sense(gpio_val, gpio_dir));
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}
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break;
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default:
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LOG_F(
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INFO,
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"ATI Rage: %s register at 0x%X set to 0x%X",
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get_reg_name(offset),
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offset & ~3,
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READ_DWORD_LE_A(&this->block_io_regs[offset & ~3]));
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}
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}
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uint32_t ATIRage::pci_cfg_read(uint32_t reg_offs, uint32_t size) {
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uint32_t res = 0;
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LOG_F(INFO, "Reading ATI Rage config space, offset = 0x%X, size=%d", reg_offs, size);
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res = size_dep_read(&this->pci_cfg[reg_offs], size);
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LOG_F(INFO, "Return value: 0x%X", res);
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return res;
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}
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void ATIRage::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size) {
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LOG_F(
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INFO,
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"Writing into ATI Rage PCI config space, offset = 0x%X, val=0x%X size=%d",
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reg_offs,
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BYTESWAP_32(value),
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size);
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switch (reg_offs) {
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case 0x10: /* BAR 0 */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR0], 0xFF000008);
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} else {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR0], value);
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}
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break;
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case 0x14: /* BAR 1: I/O space base, 256 bytes wide */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR1], 0x0000FFF1);
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} else {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR1], value);
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}
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case 0x18: /* BAR 2 */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR2], 0xFFFFF000);
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} else {
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WRITE_DWORD_BE_A(&this->pci_cfg[CFG_REG_BAR2], value);
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}
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break;
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case CFG_REG_BAR3: /* unimplemented */
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case CFG_REG_BAR4: /* unimplemented */
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case CFG_REG_BAR5: /* unimplemented */
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case CFG_EXP_BASE: /* no expansion ROM */
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WRITE_DWORD_BE_A(&this->pci_cfg[reg_offs], 0);
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break;
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default:
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size_dep_write(&this->pci_cfg[reg_offs], value, size);
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}
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}
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bool ATIRage::io_access_allowed(uint32_t offset, uint32_t* p_io_base) {
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if (!(this->pci_cfg[CFG_REG_CMD] & 1)) {
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LOG_F(WARNING, "ATI I/O space disabled in the command reg");
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return false;
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}
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uint32_t io_base = READ_DWORD_LE_A(&this->pci_cfg[CFG_REG_BAR1]) & ~3;
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if (offset < io_base || offset > (io_base + 0x100)) {
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LOG_F(WARNING, "Rage: I/O out of range, base=0x%X, offset=0x%X", io_base, offset);
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return false;
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}
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*p_io_base = io_base;
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return true;
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}
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bool ATIRage::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res) {
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uint32_t io_base;
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if (!this->io_access_allowed(offset, &io_base)) {
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return false;
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}
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*res = this->read_reg(offset - io_base, size);
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return true;
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}
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bool ATIRage::pci_io_write(uint32_t offset, uint32_t value, uint32_t size) {
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uint32_t io_base;
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if (!this->io_access_allowed(offset, &io_base)) {
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return false;
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}
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this->write_reg(offset - io_base, value, size);
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return true;
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}
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uint32_t ATIRage::read(uint32_t reg_start, uint32_t offset, int size) {
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LOG_F(INFO, "Reading reg=%X, size %d", offset, size);
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return 0;
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}
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void ATIRage::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {
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LOG_F(INFO, "Writing reg=%X, value=%X, size %d", offset, value, size);
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}
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