155 lines
5.6 KiB
C++
155 lines
5.6 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-20 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MacIO device family emulation
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Mac I/O (MIO) is a family of ASICs to bring support for Apple legacy
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I/O hardware to the PCI-based Power Macintosh. That legacy hardware has
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existed long before Power Macintosh was introduced. It includes:
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- versatile interface adapter (VIA)
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- Sander-Woz integrated machine (SWIM) that is a floppy disk controller
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- CUDA MCU for ADB, parameter RAM, realtime clock and power management support
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- serial communication controller (SCC)
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- Macintosh Enhanced SCSI Hardware (MESH)
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In the 68k Macintosh era, all this hardware was implemented using several
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custom chips. In a PCI-compatible Power Macintosh, the above devices are part
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of the MIO chip itself. MIO's functional blocks implementing virtual devices
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are called "cells", i.e. "VIA cell", "SWIM cell" etc.
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MIO itself is PCI compliant while the legacy hardware it emulates isn't.
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MIO occupies 512Kb of the PCI memory space divided into registers space and
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DMA space. Access to emulated legacy devices is accomplished by reading from/
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writing to MIO's PCI address space at predefined offsets.
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MIO includes a DMA controller that offers 15 DMA channels implementing
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Apple's own DMA protocol called descriptor-based DMA (DBDMA).
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Official documentation (that is somewhat incomplete and erroneous) can be
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found in the second chapter of the book "Macintosh Technology in the Common
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Hardware Reference Platform" by Apple Computer, Inc.
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*/
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#ifndef MACIO_H
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#define MACIO_H
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#include "awacs.h"
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#include "dbdma.h"
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#include "hwcomponent.h"
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#include "memctrlbase.h"
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#include "mmiodevice.h"
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#include "nvram.h"
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#include "pcidevice.h"
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#include "pcihost.h"
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#include "viacuda.h"
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#include <cinttypes>
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/**
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Heathrow ASIC emulation
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Author: Max Poliakovski
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Heathrow is a MIO-compliant ASIC used in the Gossamer architecture. It's
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hard-wired to PCI device number 16. Its I/O memory (512Kb) will be configured
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by the Macintosh firmware to live at 0xF3000000.
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Emulated subdevices and their offsets within Heathrow I/O space:
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----------------------------------------------------------------
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mesh(SCSI) register space: 0x00010000, DMA space: 0x00008000
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bmac(ethernet) register space: 0x00011000, DMA space: 0x00008200, 0x00008300
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escc(serial) register space: 0x00013000, size: 0x00001000
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DMA space: 0x00008400, size: 0x00000400
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escc:ch-a register space: 0x00013020, DMA space: 0x00008400, 0x00008500
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escc:ch-b register space: 0x00013000, DMA space: 0x00008600, 0x00008700
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davbus(sound) register space: 0x00014000, DMA space: 0x00008800, 0x00008900
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SWIM3(floppy) register space: 0x00015000, DMA space: 0x00008100
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NVRAM register space: 0x00060000, size: 0x00020000
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IDE register space: 0x00020000, DMA space: 0x00008b00
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VIA-CUDA register space: 0x00016000, size: 0x00002000
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*/
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class HeathrowIC : public PCIDevice {
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public:
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HeathrowIC();
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~HeathrowIC();
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bool supports_type(HWCompType type) {
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return type == HWCompType::MMIO_DEV;
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};
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/* PCI device methods */
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bool supports_io_space(void) {
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return false;
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};
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uint32_t pci_cfg_read(uint32_t reg_offs, uint32_t size);
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size);
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/* MMIO device methods */
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uint32_t read(uint32_t reg_start, uint32_t offset, int size);
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void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
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protected:
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uint32_t dma_read(uint32_t offset, int size);
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void dma_write(uint32_t offset, uint32_t value, int size);
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uint32_t mio_ctrl_read(uint32_t offset, int size);
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void mio_ctrl_write(uint32_t offset, uint32_t value, int size);
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private:
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uint8_t pci_cfg_hdr[256] = {
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0x6B,
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0x10, // vendor ID: Apple Computer Inc.
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0x10,
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0x00, // device ID: Heathrow Mac I/O
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0x00,
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0x00, // PCI command (set to 0 at power-up?)
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0x00,
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0x00, // PCI status (set to 0 at power-up?)
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0x01, // revision ID
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// class code is reported in OF property "class-code" as 0xff0000
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0x00, // standard programming
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0x00, // subclass code
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0xFF, // class code: unassigned
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0x00,
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0x00, // unknown defaults
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0x00,
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0x00 // unknown defaults
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};
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uint32_t int_mask2;
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uint32_t int_clear2;
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uint32_t int_levels2;
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uint32_t int_mask1;
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uint32_t int_clear1;
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uint32_t int_levels1;
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uint32_t feat_ctrl; // features control register
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/* device cells */
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ViaCuda* viacuda; /* VIA cell with Cuda MCU attached to it */
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NVram* nvram; /* NVRAM cell */
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AWACDevice* screamer; /* Screamer audio codec instance */
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DMAChannel* snd_out_dma;
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};
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#endif /* MACIO_H */
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