171 lines
6.7 KiB
C++
171 lines
6.7 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-20 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MPC106 (Grackle) emulation
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Author: Max Poliakovski
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Grackle IC is a combined memory and PCI controller manufactured by Motorola.
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It's the central device in the Gossamer architecture.
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Manual: https://www.nxp.com/docs/en/reference-manual/MPC106UM.pdf
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This code emulates as much functionality as needed to run PowerMac Beige G3.
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This implies that
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- we only support address map B
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- our virtual device reports revision 4.0 as expected by machine firmware
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*/
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#ifndef MPC106_H_
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#define MPC106_H_
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#include "hwcomponent.h"
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#include "memctrlbase.h"
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#include "mmiodevice.h"
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#include "pcidevice.h"
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#include "pcihost.h"
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#include <cinttypes>
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#include <unordered_map>
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class MPC106 : public MemCtrlBase, public PCIDevice, public PCIHost {
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public:
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MPC106();
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~MPC106();
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bool supports_type(HWCompType type);
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uint32_t read(uint32_t reg_start, uint32_t offset, int size);
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void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
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/* PCI host bridge API */
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bool pci_register_device(int dev_num, PCIDevice* dev_instance);
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protected:
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/* PCI access */
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uint32_t pci_read(uint32_t size);
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void pci_write(uint32_t value, uint32_t size);
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/* my own PCI configuration registers access */
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uint32_t pci_cfg_read(uint32_t reg_offs, uint32_t size);
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size);
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bool supports_io_space(void) {
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return true;
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};
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bool pci_register_mmio_region(uint32_t start_addr, uint32_t size, PCIDevice* obj);
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void setup_ram(void);
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private:
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uint8_t my_pci_cfg_hdr[256] = {
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0x57, 0x10, // vendor ID: Motorola
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0x02, 0x00, // device ID: MPC106
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0x06, 0x00, // PCI command
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0x80, 0x00, // PCI status
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0x40, // revision ID: 4.0
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0x00, // standard programming
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0x00, // subclass code: host bridge
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0x06, // class code: bridge device
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0x08, // cache line size
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0x00, // latency timer
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0x00, // header type
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0x00, // BIST Control
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0x00, // Interrupt line
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0x00, // Interrupt pin
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0x00, // MIN GNT
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0x00, // MAX LAT
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0x00, // Bus number
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0x00, // Subordinate bus number
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0x00, // Discount counter
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // Performance monitor command
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0x00, 0x00, // Performance monitor mode control
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0xFF, 0xFF,
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0x00, 0x00, 0x00, 0x00, // Performance monitor counter 0
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0x00, 0x00, 0x00, 0x00, // Performance monitor counter 1
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0x00, 0x00, 0x00, 0x00, // Performance monitor counter 2
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0x00, 0x00, 0x00, 0x00, // Performance monitor counter 3
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF,
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0x00, 0x00, // Power mgt config 1
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0x00, // Power mgt config 2
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0xCD, // default value for ODCR
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, // Memory Starting Address
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Extended Memory Starting Address
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Memory Ending Address
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Extended Memory Ending Address
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0x00, // Memory bank enable
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0xFF, 0xFF,
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0x00, // Memory page mode
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0xFF, 0xFF, 0xFF, 0xFF,
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0x10, 0x00, 0x00, 0xFF, // PICR1
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0x0C, 0x06, 0x0C, 0x00, // PICR2
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0x00, // ECC single-bit error counter
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0x00, // ECC single-bit error trigger
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0x04, // Alternate OS visible paramaters 1
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0x01, // Alternate OS visible paramaters 2
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0xFF, 0xFF, 0xFF, 0xFF,
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0x01, // Error enabling 1
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0x00, // Error detection 1
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0xFF,
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0x00, // 60x bus error status
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0x00, // Error enabling 2
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0x00, // Error detection 2
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0xFF,
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0x00, // PCI bus error status
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0x00, 0x00, 0x00, 0x00, // 60x/PCI ERROR address
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF,
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0x42, 0x00, 0xFF, 0x0F, // Emulation support config 1
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0x00, 0x00, 0x00, 0x00, // Modified memory status (no clear)
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0x20, 0x00, 0x00, 0x00, // Emulation support config 2
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0x00, 0x00, 0x00, 0x00, // Modified memory status (clear)
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0x00, 0x00, 0x02, 0xFF, // Memory ctrl config 1
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0x03, 0x00, 0x00, 0x00, // Memory ctrl config 2
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0x00, 0x00, 0x00, 0x00, // Memory ctrl config 3
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0x00, 0x00, 0x10, 0x00 // Memory ctrl config 4
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};
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uint32_t config_addr;
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// uint32_t config_data;
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std::unordered_map<int, PCIDevice*> pci_0_bus;
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std::vector<PCIDevice*> io_space_devs;
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};
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#endif
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