mirror of
https://github.com/dingusdev/dingusppc.git
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Result of running IWYU (https://include-what-you-use.org/) and applying most of the suggestions about unncessary includes and forward declarations. Was motivated by observing that <thread> was being included in ppcopcodes.cpp even though it was unused (found while researching the use of threads), but seems generally good to help with build times and correctness.
207 lines
6.3 KiB
C++
207 lines
6.3 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** Platinum Memory/Display Controller emulation. */
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#include <devices/deviceregistry.h>
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#include <devices/memctrl/platinum.h>
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#include <devices/video/displayid.h>
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#include <loguru.hpp>
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#include <cinttypes>
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using namespace Platinum;
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PlatinumCtrl::PlatinumCtrl() : MemCtrlBase()
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{
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this->name = "Platinum Memory Controller";
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supports_types(HWCompType::MEM_CTRL | HWCompType::MMIO_DEV);
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// add MMIO region for the configuration and status registers
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add_mmio_region(0xF8000000, 0x500, this);
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// determine actual VRAM size (min. 1MB, max. 4MB)
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this->vram_size = 1 << 20;
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// insert video memory region into the main memory map
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this->add_ram_region(0xF1000000UL, this->vram_size);
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// initialize the CPUID register with the following CPU:
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// PowerPC 601 @ 75 MHz, bus frequency: 37,5 MHz
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this->cpu_id = (0x3001 << 16) | ClkSrc3 | (CpuSpeed3::CPU_75_BUS_38 << 8);
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this->display_id = std::unique_ptr<DisplayID> (new DisplayID());
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}
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uint32_t PlatinumCtrl::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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if (size != 4) {
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LOG_F(WARNING, "Platinum: unsupported register access size %d!", size);
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return 0;
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}
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switch (offset) {
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case PlatinumReg::CPU_ID:
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return this->cpu_id;
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case PlatinumReg::DRAM_REFRESH:
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return this->dram_refresh;
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case PlatinumReg::BANK_0_BASE:
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case PlatinumReg::BANK_1_BASE:
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case PlatinumReg::BANK_2_BASE:
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case PlatinumReg::BANK_3_BASE:
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case PlatinumReg::BANK_4_BASE:
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case PlatinumReg::BANK_5_BASE:
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case PlatinumReg::BANK_6_BASE:
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case PlatinumReg::BANK_7_BASE:
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return this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4];
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case PlatinumReg::CACHE_CONFIG:
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return 0; // report no L2 cache installed
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case PlatinumReg::FB_BASE_ADDR:
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return this->fb_addr;
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case PlatinumReg::MON_ID_SENSE:
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LOG_F(INFO, "Platinum: display sense read");
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return (this->cur_mon_id ^ 7);
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default:
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LOG_F(WARNING, "Platinum: unknown register read at offset 0x%X", offset);
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}
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return 0;
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}
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void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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switch (offset) {
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case PlatinumReg::ROM_TIMING:
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this->rom_timing = value;
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break;
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case PlatinumReg::DRAM_TIMING:
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this->dram_timing = value;
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break;
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case PlatinumReg::DRAM_REFRESH:
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this->dram_refresh = value;
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break;
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case PlatinumReg::BANK_0_BASE:
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case PlatinumReg::BANK_1_BASE:
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case PlatinumReg::BANK_2_BASE:
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case PlatinumReg::BANK_3_BASE:
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case PlatinumReg::BANK_4_BASE:
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case PlatinumReg::BANK_5_BASE:
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case PlatinumReg::BANK_6_BASE:
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case PlatinumReg::BANK_7_BASE:
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this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4] = value;
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break;
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case PlatinumReg::FB_BASE_ADDR:
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this->fb_addr = value;
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LOG_F(INFO, "Platinum: Framebuffer address set to 0x%X", value);
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break;
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case PlatinumReg::FB_CONFIG_1:
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this->fb_config_1 = value;
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break;
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case PlatinumReg::FB_CONFIG_2:
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this->fb_config_2 = value;
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break;
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case PlatinumReg::VMEM_PAGE_MODE:
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this->vmem_fp_mode = value;
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break;
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case PlatinumReg::MON_ID_SENSE:
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LOG_F(INFO, "Platinum: display sense written with 0x%X", value);
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this->cur_mon_id = this->display_id->read_monitor_sense(value & 7, value ^ 7);
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break;
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case PlatinumReg::FB_RESET:
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this->fb_reset = value;
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break;
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case PlatinumReg::VRAM_REFRESH:
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this->vram_refresh = value;
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break;
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case PlatinumReg::SWATCH_CONFIG:
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this->swatch_config = value;
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break;
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case PlatinumReg::SWATCH_INT_MASK:
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this->swatch_int_mask = value;
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break;
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case PlatinumReg::SWATCH_HAL:
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LOG_F(INFO, "Swatch HAL set to 0x%X", value);
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break;
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case PlatinumReg::SWATCH_HFP:
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LOG_F(INFO, "Swatch HFP set to 0x%X", value);
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break;
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case PlatinumReg::SWATCH_HPIX:
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LOG_F(INFO, "Swatch HPIX set to 0x%X", value);
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break;
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case PlatinumReg::SWATCH_VAL:
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LOG_F(INFO, "Swatch VAL set to 0x%X", value);
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break;
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case PlatinumReg::SWATCH_VFP:
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LOG_F(INFO, "Swatch VFP set to 0x%X", value);
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break;
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default:
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LOG_F(WARNING, "Platinum: unknown register write at offset 0x%X", offset);
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}
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}
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void PlatinumCtrl::insert_ram_dimm(int slot_num, uint32_t capacity)
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{
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if (slot_num < 0 || slot_num >= 4) {
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ABORT_F("Platinum: invalid DIMM slot %d", slot_num);
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}
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switch (capacity) {
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case DRAM_CAP_2MB:
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case DRAM_CAP_4MB:
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case DRAM_CAP_8MB:
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case DRAM_CAP_16MB:
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case DRAM_CAP_32MB:
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case DRAM_CAP_64MB:
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this->bank_size[slot_num * 2 + 0] = capacity;
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break;
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case DRAM_CAP_128MB:
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this->bank_size[slot_num * 2 + 0] = DRAM_CAP_64MB;
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this->bank_size[slot_num * 2 + 1] = DRAM_CAP_64MB;
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break;
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default:
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ABORT_F("Platinum: unsupported DRAM capacity %d", capacity);
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}
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}
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void PlatinumCtrl::map_phys_ram()
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{
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uint32_t total_ram = 0;
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for (int i = 0; i < 8; i++) {
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total_ram += this->bank_size[i];
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}
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if (total_ram > DRAM_CAP_64MB) {
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ABORT_F("Platinum: RAM bigger than 64MB not supported yet");
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}
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if (!add_ram_region(0x00000000, total_ram)) {
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ABORT_F("Platinum: could not allocate RAM storage");
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}
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}
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static const DeviceDescription Platinum_Descriptor = {
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PlatinumCtrl::create, {}, {}
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};
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REGISTER_DEVICE(Platinum, Platinum_Descriptor);
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