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6d23e18c11
PCCard is used by PowerBook G3 Wallstreet in Open Firmware 2.0.1. CardBus is probed in New World Macs starting from at least Open Firmware 4.1.9f1 sometime after Open Firmware 3.1.1. - Create PCIBase from common stuff in PCIDevice. - Add PCIBridgeBase. These have a primary bus number, secondary bus number, and subordinate bus number which are used to determine if PCI type 1 config cycle should be passed. - Change PCIBridge to use PCIBridgeBase instead of PCIDevice. - Add PCICardBusBridge which uses PCIBridgeBase.
113 lines
4.1 KiB
C++
113 lines
4.1 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef PCI_CARDBUSBRIDGE_H
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#define PCI_CARDBUSBRIDGE_H
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#include <devices/deviceregistry.h>
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#include <devices/common/pci/pcibridgebase.h>
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#include <devices/common/pci/pcihost.h>
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#include <cinttypes>
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#include <string>
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#include <unordered_map>
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#include <vector>
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/** PCI configuration space registers offsets */
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enum {
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PCI_CFG_CB_CAPABILITIES = 0x14, // CB_CAPABILITIES.b, 0.b, CB_SEC_STATUS.w
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PCI_CFG_CB_MEMORY_BASE_0 = 0x1C,
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PCI_CFG_CB_MEMORY_LIMIT_0 = 0x20,
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PCI_CFG_CB_MEMORY_BASE_1 = 0x24,
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PCI_CFG_CB_MEMORY_LIMIT_1 = 0x28,
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PCI_CFG_CB_IO_BASE_0 = 0x2C,
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PCI_CFG_CB_IO_LIMIT_0 = 0x30,
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PCI_CFG_CB_IO_BASE_1 = 0x34,
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PCI_CFG_CB_IO_LIMIT_1 = 0x38,
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PCI_CFG_CB_SUBSYSTEM_IDS = 0x40, // CB_SUBSYSTEM_VENDOR_ID.w, CB_SUBSYSTEM_ID.w
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PCI_CFG_CB_LEGACY_MODE_BASE = 0x44,
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};
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class PCICardbusBridge : public PCIBridgeBase {
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public:
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PCICardbusBridge(std::string name);
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~PCICardbusBridge() = default;
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// PCIBase methods
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virtual uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details);
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virtual void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details);
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virtual bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res);
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virtual bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size);
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// plugin interface for using in the derived classes
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std::function<uint32_t()> pci_rd_memory_base_0;
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std::function<void(uint32_t)> pci_wr_memory_base_0;
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std::function<uint32_t()> pci_rd_memory_limit_0;
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std::function<void(uint32_t)> pci_wr_memory_limit_0;
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std::function<uint32_t()> pci_rd_memory_base_1;
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std::function<void(uint32_t)> pci_wr_memory_base_1;
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std::function<uint32_t()> pci_rd_memory_limit_1;
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std::function<void(uint32_t)> pci_wr_memory_limit_1;
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std::function<uint32_t()> pci_rd_io_base_0;
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std::function<void(uint32_t)> pci_wr_io_base_0;
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std::function<uint32_t()> pci_rd_io_limit_0;
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std::function<void(uint32_t)> pci_wr_io_limit_0;
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std::function<uint32_t()> pci_rd_io_base_1;
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std::function<void(uint32_t)> pci_wr_io_base_1;
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std::function<uint32_t()> pci_rd_io_limit_1;
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std::function<void(uint32_t)> pci_wr_io_limit_1;
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protected:
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// PCI configuration space state
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uint32_t memory_base_0 = 0;
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uint32_t memory_limit_0 = 0;
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uint32_t memory_base_1 = 0;
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uint32_t memory_limit_1 = 0;
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uint32_t io_base_0 = 0;
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uint32_t io_limit_0 = 0;
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uint32_t io_base_1 = 0;
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uint32_t io_limit_1 = 0;
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uint16_t subsys_id = 0;
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uint16_t subsys_vndr = 0;
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uint32_t legacy_mode_base = 0;
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// 0 = not writable
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uint32_t memory_0_cfg = 0xfffff000;
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uint32_t memory_1_cfg = 0xfffff000;
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// 0 = not writable, 0x0000fffc = supports 16 bit I/O range, 0xfffffffd = supports 32 bit I/O range
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uint32_t io_0_cfg = 0x0000fffc;
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uint32_t io_1_cfg = 0x0000fffc;
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// calculated address ranges
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uint32_t memory_base_0_32 = 0;
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uint32_t memory_limit_0_32 = 0;
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uint32_t memory_base_1_32 = 0;
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uint32_t memory_limit_1_32 = 0;
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uint32_t io_base_0_32 = 0;
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uint32_t io_limit_0_32 = 0;
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uint32_t io_base_1_32 = 0;
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uint32_t io_limit_1_32 = 0;
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};
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#endif /* PCI_CARDBUSBRIDGE_H */
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