mirror of
https://github.com/dingusdev/dingusppc.git
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Result of running IWYU (https://include-what-you-use.org/) and applying most of the suggestions about unncessary includes and forward declarations. Was motivated by observing that <thread> was being included in ppcopcodes.cpp even though it was unused (found while researching the use of threads), but seems generally good to help with build times and correctness.
238 lines
6.8 KiB
C++
238 lines
6.8 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <cpu/ppc/ppcemu.h>
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#include <devices/deviceregistry.h>
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#include <devices/ioctrl/macio.h>
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#include <endianswap.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <cinttypes>
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OHare::OHare() : PCIDevice("mac-io/ohare"), InterruptCtrl()
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{
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supports_types(HWCompType::MMIO_DEV | HWCompType::PCI_DEV | HWCompType::INT_CTRL);
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// populate my PCI config header
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this->vendor_id = PCI_VENDOR_APPLE;
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this->device_id = 0x0007;
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this->class_rev = 0xFF000001;
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this->cache_ln_sz = 8;
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this->setup_bars({{0, 0xFFF80000UL}}); // declare 512Kb of memory-mapped I/O space
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this->pci_notify_bar_change = [this](int bar_num) {
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this->notify_bar_change(bar_num);
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};
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// NVRAM connection
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this->nvram = dynamic_cast<NVram*>(gMachineObj->get_comp_by_name("NVRAM"));
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// connect Cuda
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this->viacuda = dynamic_cast<ViaCuda*>(gMachineObj->get_comp_by_name("ViaCuda"));
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// initialize sound chip and its DMA output channel, then wire them together
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this->awacs = std::unique_ptr<AwacsScreamer> (new AwacsScreamer());
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this->snd_out_dma = std::unique_ptr<DMAChannel> (new DMAChannel());
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this->awacs->set_dma_out(this->snd_out_dma.get());
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this->snd_out_dma->set_callbacks(
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std::bind(&AwacsScreamer::dma_out_start, this->awacs.get()),
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std::bind(&AwacsScreamer::dma_out_stop, this->awacs.get())
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);
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// connect serial HW
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this->escc = dynamic_cast<EsccController*>(gMachineObj->get_comp_by_name("Escc"));
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}
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void OHare::notify_bar_change(int bar_num)
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{
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if (bar_num) // only BAR0 is supported
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return;
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if (this->base_addr != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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if (this->base_addr) {
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LOG_F(WARNING, "%s: deallocating I/O memory not implemented",
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this->pci_name.c_str());
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}
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this->base_addr = this->bars[0] & 0xFFFFFFF0UL;
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this->host_instance->pci_register_mmio_region(this->base_addr, 0x80000, this);
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LOG_F(INFO, "%s: base address set to 0x%X", this->pci_name.c_str(), this->base_addr);
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}
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}
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uint32_t OHare::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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unsigned sub_addr = (offset >> 12) & 0x7F;
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switch (sub_addr) {
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case 0:
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return read_ctrl(offset, size);
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case 8:
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return dma_read(offset & 0x7FFF, size);
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case 0x13: // ESCC MacRISC addressing
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return this->escc->read((offset >> 4) & 0xF);
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case 0x14: // AWACS
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return this->awacs->snd_ctrl_read(offset & 0xFF, size);
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case 0x16:
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case 0x17:
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return this->viacuda->read((offset >> 9) & 0xF);
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case 0x20:
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return 0xFF7FU;
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default:
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if (sub_addr >= 0x60) {
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return this->nvram->read_byte((offset - 0x60000) >> 4);
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} else {
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LOG_F(WARNING, "OHare: read from unimplemented register 0x%X",
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this->base_addr + offset);
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}
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}
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return 0xFFFFFFFFUL;
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}
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void OHare::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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unsigned sub_addr = (offset >> 12) & 0x7F;
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switch (sub_addr) {
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case 0:
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this->write_ctrl(offset, value, size);
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break;
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case 8:
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this->dma_write(offset & 0x7FFF, value, size);
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break;
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case 0x13: // ESCC MacRISC addressing
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this->escc->write((offset >> 4) & 0xF, value);
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break;
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case 0x14: // AWACS
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this->awacs->snd_ctrl_write(offset & 0xFF, value, size);
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break;
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case 0x16:
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case 0x17: // VIA-CUDA
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this->viacuda->write((offset >> 9) & 0xF, value);
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break;
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case 0x20:
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LOG_F(INFO, "OHare: write to IDE0 register at 0x%X", offset);
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break;
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default:
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if (sub_addr >= 0x60) {
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this->nvram->write_byte((offset - 0x60000) >> 4, value);
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} else {
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LOG_F(WARNING, "OHare: writing to unimplemented device register 0x%X",
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this->base_addr + offset);
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}
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}
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}
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uint32_t OHare::read_ctrl(uint32_t offset, int size)
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{
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uint32_t res = 0;
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switch (offset & 0xFC) {
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case MIO_INT_EVENTS1:
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res = this->int_events;
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break;
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case MIO_OHARE_ID: // HACK: no clue what this register is supposed to contain
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res = 0xFFFFBFFFUL;
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default:
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LOG_F(WARNING, "OHare: read from unknown control register at %x", offset);
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break;
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}
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return BYTESWAP_32(res);
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}
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void OHare::write_ctrl(uint32_t offset, uint32_t value, int size)
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{
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switch (offset) {
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case MIO_INT_MASK1:
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this->int_mask = BYTESWAP_32(value);
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break;
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case MIO_INT_CLEAR1:
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if (value & MACIO_INT_CLR) {
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this->int_events = 0;
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this->cpu_int_latch = false;
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ppc_release_int();
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LOG_F(5, "OHare: CPU INT latch cleared");
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} else {
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this->int_events &= BYTESWAP_32(value);
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}
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break;
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default:
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LOG_F(WARNING, "OHare: writing to unimplemented control register 0x%X",
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this->base_addr + offset);
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}
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}
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uint32_t OHare::dma_read(uint32_t offset, int size)
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{
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switch (offset >> 8) {
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case 8:
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return this->snd_out_dma->reg_read(offset & 0xFF, size);
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default:
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LOG_F(WARNING, "OHare: unsupported DMA channel read, offset=0x%X", offset);
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}
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return 0xFFFFFFUL;
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}
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void OHare::dma_write(uint32_t offset, uint32_t value, int size)
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{
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switch (offset >> 8) {
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case 8:
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this->snd_out_dma->reg_write(offset & 0xFF, value, size);
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break;
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default:
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LOG_F(WARNING, "OHare: unsupported DMA channel write, offset=0x%X, val=0x%X", offset, value);
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}
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}
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uint32_t OHare::register_dev_int(IntSrc src_id)
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{
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return 0;
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}
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uint32_t OHare::register_dma_int(IntSrc src_id)
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{
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return 0;
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}
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void OHare::ack_int(uint32_t irq_id, uint8_t irq_line_state)
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{
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}
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void OHare::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state)
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{
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}
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static const vector<string> OHare_Subdevices = {
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"NVRAM", "ViaCuda", "Scsi0", "Mesh", "Escc", "Swim3"
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};
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static const DeviceDescription OHare_Descriptor = {
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OHare::create, OHare_Subdevices, {}
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};
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REGISTER_DEVICE(OHare, OHare_Descriptor);
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