mirror of
https://github.com/dingusdev/dingusppc.git
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275 lines
8.1 KiB
C++
275 lines
8.1 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <cpu/ppc/ppcemu.h>
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#include <devices/common/dbdma.h>
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#include <devices/common/viacuda.h>
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#include <devices/ioctrl/macio.h>
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#include <devices/sound/awacs.h>
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#include <machines/machinebase.h>
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#include <cinttypes>
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#include <functional>
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#include <iostream>
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#include <loguru.hpp>
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/** Heathrow Mac I/O device emulation.
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Author: Max Poliakovski
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*/
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using namespace std;
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HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow") {
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this->nvram = new NVram();
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this->viacuda = new ViaCuda();
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gMachineObj->add_subdevice("ViaCuda", this->viacuda);
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// initialize sound chip and its DMA output channel, then wire them together
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this->screamer = new AwacsScreamer();
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this->snd_out_dma = new DMAChannel();
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this->screamer->set_dma_out(this->snd_out_dma);
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this->snd_out_dma->set_callbacks(
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std::bind(&AwacsScreamer::dma_start, this->screamer),
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std::bind(&AwacsScreamer::dma_end, this->screamer)
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);
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this->mesh = new MESHController(HeathrowMESHID);
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}
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HeathrowIC::~HeathrowIC() {
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if (this->nvram)
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delete (this->nvram);
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if (this->viacuda)
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delete (this->viacuda);
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if (this->mesh)
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delete (this->mesh);
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}
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uint32_t HeathrowIC::pci_cfg_read(uint32_t reg_offs, uint32_t size) {
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return this->pci_cfg_hdr[reg_offs & 0xFF];
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}
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void HeathrowIC::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size) {
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switch (reg_offs) {
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case CFG_REG_BAR0: // base address register
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value = LE2BE(value);
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if (value == 0xFFFFFFFF) {
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LOG_F(
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ERROR,
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"%s err: BAR0 block size determination not \
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implemented yet \n",
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this->name.c_str());
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} else if (value & 1) {
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LOG_F(ERROR, "%s err: BAR0 I/O space not supported! \n", this->name.c_str());
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} else if (value & 0x06) {
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LOG_F(ERROR, "%s err: BAR0 64-bit I/O space not supported! \n", this->name.c_str());
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} else {
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this->base_addr = value & 0xFFF80000;
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this->host_instance->pci_register_mmio_region(this->base_addr, 0x80000, this);
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LOG_F(INFO, "%s base address set to %x \n", this->name.c_str(), this->base_addr);
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}
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break;
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}
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}
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uint32_t HeathrowIC::dma_read(uint32_t offset, int size) {
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uint32_t res = 0;
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switch (offset >> 8) {
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case 8:
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res = this->snd_out_dma->reg_read(offset & 0xFF, size);
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break;
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default:
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LOG_F(WARNING, "Unsupported DMA channel read, offset=0x%X", offset);
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}
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return res;
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}
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void HeathrowIC::dma_write(uint32_t offset, uint32_t value, int size) {
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switch (offset >> 8) {
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case 8:
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this->snd_out_dma->reg_write(offset & 0xFF, value, size);
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break;
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default:
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LOG_F(WARNING, "Unsupported DMA channel write, offset=0x%X, val=0x%X", offset, value);
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}
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}
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uint32_t HeathrowIC::read(uint32_t reg_start, uint32_t offset, int size) {
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uint32_t res = 0;
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LOG_F(9, "%s: reading from offset %x \n", this->name.c_str(), offset);
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unsigned sub_addr = (offset >> 12) & 0x7F;
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switch (sub_addr) {
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case 0:
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res = mio_ctrl_read(offset, size);
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break;
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case 8:
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res = dma_read(offset - 0x8000, size);
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break;
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case 0x10:
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res = this->mesh->read((offset >> 4) & 0xF);
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break;
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case 0x14:
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res = this->screamer->snd_ctrl_read(offset - 0x14000, size);
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break;
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case 0x16:
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case 0x17:
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res = this->viacuda->read((offset - 0x16000) >> 9);
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break;
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default:
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if (sub_addr >= 0x60) {
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res = this->nvram->read_byte((offset - 0x60000) >> 4);
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} else {
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LOG_F(WARNING, "Attempting to read unmapped I/O space: %x \n", offset);
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}
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}
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return res;
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}
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void HeathrowIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {
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LOG_F(9, "%s: writing to offset %x \n", this->name.c_str(), offset);
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unsigned sub_addr = (offset >> 12) & 0x7F;
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switch (sub_addr) {
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case 0:
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mio_ctrl_write(offset, value, size);
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break;
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case 8:
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dma_write(offset - 0x8000, value, size);
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break;
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case 0x10:
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this->mesh->write((offset >> 4) & 0xF, value);
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break;
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case 0x14:
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this->screamer->snd_ctrl_write(offset - 0x14000, value, size);
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break;
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case 0x16:
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case 0x17:
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this->viacuda->write((offset - 0x16000) >> 9, value);
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break;
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default:
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if (sub_addr >= 0x60) {
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this->nvram->write_byte((offset - 0x60000) >> 4, value);
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} else {
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LOG_F(WARNING, "Attempting to write to unmapped I/O space: %x \n", offset);
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}
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}
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}
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uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size) {
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uint32_t res = 0;
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switch (offset & 0xFC) {
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case 0x14:
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LOG_F(9, "read from MIO:Int_Mask2 register \n");
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res = this->int_mask2;
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break;
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case 0x18:
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LOG_F(9, "read from MIO:Int_Clear2 register \n");
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res = this->int_clear2;
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break;
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case 0x1C:
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LOG_F(9, "read from MIO:Int_Levels2 register \n");
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res = this->int_levels2;
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break;
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case 0x24:
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LOG_F(9, "read from MIO:Int_Mask1 register \n");
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res = this->int_mask1;
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break;
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case 0x28:
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LOG_F(9, "read from MIO:Int_Clear1 register \n");
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res = this->int_clear1;
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break;
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case 0x2C:
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LOG_F(9, "read from MIO:Int_Levels1 register \n");
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res = this->int_levels1;
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break;
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case 0x34: /* heathrowIDs / HEATHROW_MBCR (Linux): media bay config reg? */
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LOG_F(9, "read from MIO:ID register at Address %x \n", ppc_state.pc);
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res = this->macio_id;
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break;
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case 0x38:
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LOG_F(9, "read from MIO:Feat_Ctrl register \n");
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res = this->feat_ctrl;
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break;
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default:
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LOG_F(WARNING, "read from unknown MIO register at %x \n", offset);
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break;
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}
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return res;
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}
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void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
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switch (offset & 0xFC) {
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case 0x14:
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LOG_F(9, "write %x to MIO:Int_Mask2 register \n", value);
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this->int_mask2 = value;
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break;
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case 0x18:
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LOG_F(9, "write %x to MIO:Int_Clear2 register \n", value);
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this->int_clear2 = value;
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break;
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case 0x1C:
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LOG_F(9, "write %x to MIO:Int_Levels2 register \n", value);
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this->int_levels2 = value;
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break;
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case 0x24:
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LOG_F(9, "write %x to MIO:Int_Mask1 register \n", value);
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this->int_mask1 = value;
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break;
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case 0x28:
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LOG_F(9, "write %x to MIO:Int_Clear1 register \n", value);
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this->int_clear1 = value;
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break;
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case 0x2C:
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LOG_F(9, "write %x to MIO:Int_Levels1 register \n", value);
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this->int_levels1 = value;
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break;
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case 0x34:
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LOG_F(WARNING, "Attempted to write %x to MIO:ID at %x; Address : %x \n", value, offset, ppc_state.pc);
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break;
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case 0x38:
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LOG_F(9, "write %x to MIO:Feat_Ctrl register \n", value);
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this->feat_ctrl = value;
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break;
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case 0x3C:
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LOG_F(9, "write %x to MIO:Aux_Ctrl register \n", value);
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this->aux_ctrl = value;
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break;
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default:
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LOG_F(WARNING, "write %x to unknown MIO register at %x \n", value, offset);
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break;
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}
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}
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