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https://github.com/dingusdev/dingusppc.git
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2a64f547cc
While dingusppc only emulates 32-bit Macs (for now), it is possible for a 32-bit Power Mac to use a PCIe card that has 64-bit BARs. finish_config_bars is added to scan the cfg values of the BARs and determine their type. The type is stored separately so that it does not need to be determined again. The type can be I/O (16 or 32 bit) or Mem (20 or 32 or 64 bit). A 64 bit bar is two BARs, the second contains the most significant 32 bits. set_bar_value uses the stored type instead of trying to determine the type itself. It is always called even when the firmware is doing sizing. For sizing, It does the job of setting the bar value so do_bar_sizing is now just a stub. Every PCIDevice that has a BAR needs to call finish_config_bars after setting up the cfg values just as they need to setup the cfg values. Since they need to do both, maybe the cfg values should be arguments of finish_config_bars, then finish_config_bars() should be renamed config_bars().
230 lines
8.2 KiB
C++
230 lines
8.2 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef PCI_DEVICE_H
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#define PCI_DEVICE_H
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#include <devices/common/mmiodevice.h>
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#include <devices/common/pci/pcihost.h>
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#include <cinttypes>
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#include <functional>
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#include <memory>
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#include <string>
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/** PCI configuration space registers offsets */
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enum {
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PCI_CFG_DEV_ID = 0x00, // device and vendor IDs
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PCI_CFG_STAT_CMD = 0x04, // command/status register
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PCI_CFG_CLASS_REV = 0x08, // class code and revision ID
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PCI_CFG_DWORD_3 = 0x0C, // BIST, HeaderType, Lat_Timer and Cache_Line_Size
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PCI_CFG_BAR0 = 0x10, // base address register 0
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PCI_CFG_BAR1 = 0x14, // base address register 1
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PCI_CFG_BAR2 = 0x18, // base address register 2
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PCI_CFG_BAR3 = 0x1C, // base address register 3
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PCI_CFG_BAR4 = 0x20, // base address register 4
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PCI_CFG_BAR5 = 0x24, // base address register 5
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PCI_CFG_CIS_PTR = 0x28, // Cardbus CIS Pointer
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PCI_CFG_SUBSYS_ID = 0x2C, // Subsysten IDs
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PCI_CFG_ROM_BAR = 0x30, // expansion ROM base address
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PCI_CFG_CAP_PTR = 0x34, // capabilities pointer
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PCI_CFG_DWORD_14 = 0x38, // reserved
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PCI_CFG_DWORD_15 = 0x3C, // Max_Lat, Min_Gnt, Int_Pin and Int_Line registers
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};
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/** PCI Vendor IDs for devices used in Power Macintosh computers. */
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enum {
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PCI_VENDOR_ATI = 0x1002,
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PCI_VENDOR_MOTOROLA = 0x1057,
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PCI_VENDOR_APPLE = 0x106B,
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PCI_VENDOR_NVIDIA = 0x10DE,
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};
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/** PCI BAR types */
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enum PCIBarType {
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BAR_Unused,
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BAR_IO_16Bit,
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BAR_IO_32Bit,
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BAR_MEM_20Bit, // < 1M
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BAR_MEM_32Bit,
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BAR_MEM_64Bit,
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BAR_MEM_64BitHi,
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};
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class PCIDevice : public MMIODevice {
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public:
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PCIDevice(std::string name);
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virtual ~PCIDevice() = default;
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virtual bool supports_io_space() {
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return false;
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};
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/* I/O space access methods */
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virtual bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res) {
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return false;
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};
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virtual bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size) {
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return false;
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};
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// configuration space access methods
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virtual uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details);
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virtual void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details);
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// plugin interface for using in the derived classes
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std::function<uint16_t()> pci_rd_stat;
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std::function<void(uint16_t)> pci_wr_stat;
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std::function<uint16_t()> pci_rd_cmd;
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std::function<void(uint16_t)> pci_wr_cmd;
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std::function<uint8_t()> pci_rd_bist;
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std::function<void(uint8_t)> pci_wr_bist;
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std::function<uint8_t()> pci_rd_lat_timer;
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std::function<void(uint8_t)> pci_wr_lat_timer;
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std::function<uint8_t()> pci_rd_cache_lnsz;
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std::function<void(uint8_t)> pci_wr_cache_lnsz;
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std::function<void(int)> pci_notify_bar_change;
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int attach_exp_rom_image(const std::string img_path);
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virtual void set_host(PCIHost* host_instance) {
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this->host_instance = host_instance;
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};
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// MMIODevice methods
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virtual uint32_t read(uint32_t rgn_start, uint32_t offset, int size) { return 0; }
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virtual void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) { }
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protected:
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void do_bar_sizing(int bar_num);
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void set_bar_value(int bar_num, uint32_t value);
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void finish_config_bars();
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void map_exp_rom_mem();
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std::string pci_name; // human-readable device name
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PCIHost* host_instance; // host bridge instance to call back
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// PCI configuration space state
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uint16_t vendor_id;
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uint16_t device_id;
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uint32_t class_rev; // class code and revision id
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uint16_t status = 0;
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uint16_t command = 0;
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uint8_t hdr_type = 0; // header type
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uint8_t lat_timer = 0; // latency timer
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uint8_t cache_ln_sz = 0; // cache line size
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uint16_t subsys_id = 0;
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uint16_t subsys_vndr = 0;
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uint8_t cap_ptr = 0;
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uint8_t max_lat = 0;
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uint8_t min_gnt = 0;
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uint8_t irq_pin = 0;
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uint8_t irq_line = 0;
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uint32_t bars[6] = { 0 }; // base address registers
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uint32_t bars_cfg[6] = { 0 }; // configuration values for base address registers
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PCIBarType bars_typ[6] = { BAR_Unused }; // types for base address registers
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uint32_t exp_bar_cfg = 0; // expansion ROM configuration
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uint32_t exp_rom_bar = 0; // expansion ROM base address register
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uint32_t exp_rom_addr = 0; // expansion ROM base address
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uint32_t exp_rom_size = 0; // expansion ROM size in bytes
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std::unique_ptr<uint8_t[]> exp_rom_data;
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};
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inline uint32_t pci_cfg_log(uint32_t value, AccessDetails &details) {
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switch (details.size << 2 | details.offset) {
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case 0x04: return (uint8_t) value;
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case 0x05: return (uint8_t)(value >> 8);
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case 0x06: return (uint8_t)(value >> 16);
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case 0x07: return (uint8_t)(value >> 24);
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case 0x08: return (uint16_t) value;
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case 0x09: return (uint16_t) (value >> 8);
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case 0x0a: return (uint16_t) (value >> 16);
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case 0x0b: return (uint16_t)((value >> 24) | (value << 8));
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case 0x10: return value;
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case 0x11: return (value >> 8) | (value << 24);
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case 0x12: return (value >> 16) | (value << 16);
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case 0x13: return (value >> 24) | (value << 8);
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default: return 0xffffffff;
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}
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}
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#define SIZE_ARGS details.size == 4 ? 'l' : details.size == 2 ? 'w' : details.size == 1 ? 'b' : '0' + details.size
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#define LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER() \
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do { if ((details.flags & PCI_CONFIG_DIRECTION) == PCI_CONFIG_READ) { \
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VLOG_F( \
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(~-details.size & details.offset) ? loguru::Verbosity_ERROR : loguru::Verbosity_WARNING, \
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"%s: read unimplemented config register @%02x.%c", \
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this->name.c_str(), reg_offs + details.offset, \
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SIZE_ARGS \
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); \
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} } while(0)
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#define LOG_NAMED_CONFIG_REGISTER(reg_verb, reg_name) \
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VLOG_F( \
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(~-details.size & details.offset) ? loguru::Verbosity_ERROR : loguru::Verbosity_WARNING, \
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"%s: %s %s register @%02x.%c = %0*x", \
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this->name.c_str(), reg_verb, reg_name, reg_offs + details.offset, \
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SIZE_ARGS, \
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details.size * 2, pci_cfg_log(value, details) \
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)
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#define LOG_READ_NAMED_CONFIG_REGISTER(reg_name) \
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do { if ((details.flags & PCI_CONFIG_DIRECTION) == PCI_CONFIG_READ) { \
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LOG_NAMED_CONFIG_REGISTER("read ", reg_name); \
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} } while(0)
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#define LOG_WRITE_NAMED_CONFIG_REGISTER(reg_name) \
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LOG_NAMED_CONFIG_REGISTER("write", reg_name)
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#define LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER_WITH_VALUE() \
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LOG_READ_NAMED_CONFIG_REGISTER("unimplemented config")
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#define LOG_WRITE_UNIMPLEMENTED_CONFIG_REGISTER() \
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LOG_WRITE_NAMED_CONFIG_REGISTER("unimplemented config")
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#define LOG_READ_NON_EXISTENT_PCI_DEVICE() \
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LOG_F( \
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ERROR, \
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"%s err: read attempt from non-existent PCI device %02x:%02x.%x @%02x.%c", \
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + details.offset, \
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SIZE_ARGS \
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)
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#define LOG_WRITE_NON_EXISTENT_PCI_DEVICE() \
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LOG_F( \
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ERROR, \
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"%s err: write attempt to non-existent PCI device %02x:%02x.%x @%02x.%c = %0*x", \
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + details.offset, \
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SIZE_ARGS, \
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details.size * 2, BYTESWAP_SIZED(value, details.size) \
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)
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#endif /* PCI_DEVICE_H */
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