mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-07-05 13:28:56 +00:00
2a64f547cc
While dingusppc only emulates 32-bit Macs (for now), it is possible for a 32-bit Power Mac to use a PCIe card that has 64-bit BARs. finish_config_bars is added to scan the cfg values of the BARs and determine their type. The type is stored separately so that it does not need to be determined again. The type can be I/O (16 or 32 bit) or Mem (20 or 32 or 64 bit). A 64 bit bar is two BARs, the second contains the most significant 32 bits. set_bar_value uses the stored type instead of trying to determine the type itself. It is always called even when the firmware is doing sizing. For sizing, It does the job of setting the bar value so do_bar_sizing is now just a stub. Every PCIDevice that has a BAR needs to call finish_config_bars after setting up the cfg values just as they need to setup the cfg values. Since they need to do both, maybe the cfg values should be arguments of finish_config_bars, then finish_config_bars() should be renamed config_bars().
381 lines
13 KiB
C++
381 lines
13 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file TNT on-board video output emulation. */
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/** TNT on-board video comprises several components:
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- Chaos ASIC that provides data bus buffering between the video subsystem
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and the processor bus
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- Control ASIC that provides addressing and control for the video subsystem
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- RaDACal RAMDAC ASIC for generating video stream to the monitor
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- Athens clock generator for generating pixel clock
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Kudos to joevt#3510 for his precious technical help and HW hacking.
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*/
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#include <core/timermanager.h>
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#include <devices/common/i2c/athens.h>
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#include <devices/common/i2c/i2c.h>
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#include <devices/deviceregistry.h>
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#include <devices/video/control.h>
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#include <endianswap.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <machines/machineproperties.h>
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#include <memaccess.h>
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#include <cinttypes>
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ControlVideo::ControlVideo()
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: PCIDevice("Control-Video"), VideoCtrlBase(640, 480)
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{
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supports_types(HWCompType::PCI_HOST | HWCompType::PCI_DEV);
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// get VRAM size in MBs and convert it to bytes
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this->vram_size = GET_INT_PROP("gfxmem_size") << 20;
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// allocate VRAM
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this->vram_ptr = std::unique_ptr<uint8_t[]> (new uint8_t[this->vram_size]);
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// set up PCI configuration space header
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this->vendor_id = PCI_VENDOR_APPLE;
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this->device_id = 3;
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this->class_rev = 0;
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this->bars_cfg[0] = 0xFFFFFFFFUL; // I/O region (4 bytes but it's weird because bit 1 is set)
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this->bars_cfg[1] = 0xFFFFF000UL; // base address for the HW registers (4KB)
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this->bars_cfg[2] = 0xFC000000UL; // base address for the VRAM (64MB)
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this->finish_config_bars();
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this->pci_notify_bar_change = [this](int bar_num) {
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this->notify_bar_change(bar_num);
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};
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// initialize the video clock generator
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this->clk_gen = std::unique_ptr<AthensClocks> (new AthensClocks(0x28));
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// register the video clock generator with the I2C host
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I2CBus* i2c_bus = dynamic_cast<I2CBus*>(gMachineObj->get_comp_by_type(HWCompType::I2C_HOST));
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i2c_bus->register_device(0x28, this->clk_gen.get());
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// register RaDACal with the I/O controller
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GrandCentral* gc_obj = dynamic_cast<GrandCentral*>(gMachineObj->get_comp_by_name("GrandCentral"));
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gc_obj->attach_iodevice(1, this);
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// initialize display identification
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this->display_id = std::unique_ptr<DisplayID> (new DisplayID());
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}
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void ControlVideo::notify_bar_change(int bar_num)
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{
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switch (bar_num) {
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case 0:
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this->io_base = this->bars[bar_num] & ~3;
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LOG_F(INFO, "Control: I/O space address set to 0x%08X", this->io_base);
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break;
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case 1:
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if (this->regs_base != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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this->regs_base = this->bars[bar_num] & 0xFFFFFFF0UL;
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this->host_instance->pci_register_mmio_region(this->regs_base,
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0x1000, this);
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LOG_F(INFO, "Control: register aperture set to 0x%08X", this->regs_base);
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}
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break;
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case 2:
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if (this->vram_base != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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this->vram_base = this->bars[bar_num] & 0xFFFFFFF0UL;
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this->host_instance->pci_register_mmio_region(this->vram_base,
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0x04000000, this);
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LOG_F(INFO, "Control: VRAM aperture set to 0x%08X", this->vram_base);
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}
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break;
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}
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}
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uint32_t ControlVideo::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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uint32_t result = 0;
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if (rgn_start == this->vram_base) {
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if (offset >= 0x800000) {
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return read_mem_rev(&this->vram_ptr[offset - 0x800000], size);
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} else {
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LOG_F(INFO, "Control: little-endian access to VRAM not supported yet");
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return 0;
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}
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}
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if (rgn_start == this->regs_base) {
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switch (offset >> 4) {
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case ControlRegs::TEST:
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result = this->test;
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break;
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case ControlRegs::MON_SENSE:
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result = this->cur_mon_id << 6;
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break;
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default:
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LOG_F(INFO, "read from 0x%08X:0x%08X", rgn_start, offset);
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}
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return BYTESWAP_32(result);
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}
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return 0;
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}
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void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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if (rgn_start == this->vram_base) {
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if (offset >= 0x800000) {
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write_mem_rev(&this->vram_ptr[offset - 0x800000], value, size);
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} else {
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LOG_F(INFO, "Control: little-endian access to VRAM not supported yet");
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}
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return;
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}
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if (rgn_start == this->regs_base) {
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value = BYTESWAP_32(value);
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switch (offset >> 4) {
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case ControlRegs::VFPEQ:
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case ControlRegs::VFP:
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case ControlRegs::VAL:
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case ControlRegs::VBP:
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case ControlRegs::VBPEQ:
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case ControlRegs::VSYNC:
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case ControlRegs::VHLINE:
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case ControlRegs::PIPED:
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case ControlRegs::HPIX:
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case ControlRegs::HFP:
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case ControlRegs::HAL:
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case ControlRegs::HBWAY:
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case ControlRegs::HSP:
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case ControlRegs::HEQ:
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case ControlRegs::HLFLN:
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case ControlRegs::HSERR:
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this->swatch_params[(offset >> 4) - 1] = value;
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break;
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case ControlRegs::TEST:
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if (this->test != value) {
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if ((this->test & ~TEST_STROBE) != (value & ~TEST_STROBE)) {
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this->test = value;
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this->test_shift = 0;
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LOG_F(9, "New TEST value: 0x%08X", this->test);
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} else {
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LOG_F(9, "TEST strobe bit flipped, new value: 0x%08X", value);
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this->test = value;
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if (++this->test_shift >= 3) {
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LOG_F(9, "Received TEST reg value: 0x%08X", this->test & ~TEST_STROBE);
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if ((this->test ^ this->prev_test) & 0x400) {
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if (this->test & 0x400) {
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this->disable_display();
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} else {
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this->enable_display();
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}
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this->prev_test = this->test;
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}
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}
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}
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}
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break;
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case ControlRegs::GBASE:
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this->fb_base = value;
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break;
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case ControlRegs::ROW_WORDS:
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this->row_words = value;
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break;
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case ControlRegs::MON_SENSE:
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LOG_F(9, "Control: monitor sense written with 0x%X", value);
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value = (value >> 3) & 7;
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this->cur_mon_id = this->display_id->read_monitor_sense(value & 7, value ^ 7);
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break;
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case ControlRegs::ENABLE:
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this->flags = value;
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break;
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case ControlRegs::GSC_DIVIDE:
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this->clock_divider = value;
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break;
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case ControlRegs::REFRESH_COUNT:
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LOG_F(INFO, "Control: refresh count set to 0x%08X", value);
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break;
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case ControlRegs::INT_ENABLE:
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this->int_enable = value;
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break;
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default:
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LOG_F(INFO, "write 0x%08X to 0x%08X:0x%08X", value, rgn_start, offset);
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}
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}
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}
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void ControlVideo::enable_display()
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{
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int new_width, new_height, hori_blank, vert_blank, clk_divisor;
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// get pixel frequency from Athens
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this->pixel_clock = this->clk_gen->get_dot_freq();
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// get RaDACal clock divisor
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clk_divisor = 1 << ((rad_cr >> 6) + 1);
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// calculate active_width and active_height from video timing parameters
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new_width = swatch_params[ControlRegs::HFP-1] - swatch_params[ControlRegs::HAL-1];
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new_height = swatch_params[ControlRegs::VFP-1] - swatch_params[ControlRegs::VAL-1];
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new_width *= clk_divisor;
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new_height >>= 1; // FIXME: assume non-interlaced mode for now
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if (new_width != this->active_width || new_height != this->active_height) {
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LOG_F(WARNING, "Display window resizing not implemented yet!");
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}
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this->active_width = new_width;
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this->active_height = new_height;
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// get pixel depth from RaDACal
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switch ((this->rad_cr >> 2) & 3) {
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case 0:
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this->pixel_depth = 8;
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break;
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case 1:
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this->pixel_depth = 16;
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break;
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case 2:
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this->pixel_depth = 32;
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break;
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default:
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ABORT_F("Invalid RaDACal pixel depth code!");
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}
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if (pixel_depth == 8) {
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this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
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this->convert_frame_8bpp(dst_buf, dst_pitch);
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};
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} else {
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ABORT_F("Control: 16bpp and 32bpp formats not supported yet!");
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}
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// set framebuffer parameters
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this->fb_ptr = &this->vram_ptr[this->fb_base];
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this->fb_pitch = this->row_words;
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// calculate display refresh rate
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hori_blank = swatch_params[ControlRegs::HAL-1] +
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(swatch_params[ControlRegs::HSP-1] - swatch_params[ControlRegs::HFP-1]);
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hori_blank *= clk_divisor;
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vert_blank = swatch_params[ControlRegs::VAL-1] +
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(swatch_params[ControlRegs::VSYNC-1] - swatch_params[ControlRegs::VFP-1]);
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vert_blank >>= 1;
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this->refresh_rate = (double)(this->pixel_clock) / (new_width + hori_blank)
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/ (new_height + vert_blank);
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LOG_F(INFO, "Control: refresh rate set to %f Hz", this->refresh_rate);
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// set up periodic timer for display updates
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uint64_t refresh_interval = static_cast<uint64_t>(1.0f / refresh_rate * NS_PER_SEC + 0.5);
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TimerManager::get_instance()->add_cyclic_timer(
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refresh_interval,
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[this]() {
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this->update_screen();
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}
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);
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this->update_screen();
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LOG_F(INFO, "Control: display enabled");
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this->crtc_on = true;
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}
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void ControlVideo::disable_display()
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{
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this->crtc_on = false;
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LOG_F(INFO, "Control: display disabled");
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}
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// ========================== RaDACal related stuff ==========================
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uint16_t ControlVideo::iodev_read(uint32_t address)
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{
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LOG_F(INFO, "RaDACal: read from 0x%08X", address);
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return 0;
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}
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void ControlVideo::iodev_write(uint32_t address, uint16_t value)
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{
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switch (address) {
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case RadacalRegs::ADDRESS:
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this->rad_addr = value;
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this->comp_index = 0;
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break;
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case RadacalRegs::CURSOR_DATA:
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break;
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case RadacalRegs::MULTI:
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switch (this->rad_addr) {
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case RadacalRegs::CURSOR_POS_HI:
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this->rad_cur_pos_hi = value;
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break;
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case RadacalRegs::CURSOR_POS_LO:
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this->rad_cur_pos_lo = value;
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break;
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case RadacalRegs::MISC_CTRL:
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this->rad_cr = value;
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break;
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case RadacalRegs::DBL_BUF_CTRL:
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this->rad_dbl_buf_cr = value;
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break;
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default:
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LOG_F(ERROR, "Unsupported RaDACal register %d", this->rad_addr);
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}
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break;
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case RadacalRegs::CLUT_DATA:
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this->clut_color[this->comp_index++] = value;
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if (this->comp_index >= 3) {
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// TODO: combine separate components into a single ARGB value
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this->palette[this->rad_addr][0] = this->clut_color[0];
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this->palette[this->rad_addr][1] = this->clut_color[1];
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this->palette[this->rad_addr][2] = this->clut_color[2];
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this->palette[this->rad_addr][3] = 255;
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this->rad_addr++; // auto-increment CLUT address
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this->comp_index = 0;
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}
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break;
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default:
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LOG_F(INFO, "RaDACal: write to non-existent register at 0x%08X", address);
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}
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}
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// ========================== Device registry stuff ==========================
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static const PropMap Control_Properties = {
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{"gfxmem_size",
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new IntProperty( 2, vector<uint32_t>({2, 4}))},
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{"mon_id",
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new StrProperty("AppleVision1710")},
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};
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static const DeviceDescription Control_Descriptor = {
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ControlVideo::create, {}, Control_Properties
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};
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REGISTER_DEVICE(ControlVideo, Control_Descriptor);
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