145 lines
5.9 KiB
C++
145 lines
5.9 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef PCI_BRIDGE_H
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#define PCI_BRIDGE_H
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#include <devices/common/pci/pcidevice.h>
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#include <devices/common/pci/pcihost.h>
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#include <cinttypes>
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#include <string>
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/** PCI configuration space registers offsets */
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enum {
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PCI_CFG_PRIMARY_BUS = 0x18, // PRIMARY_BUS, SECONDARY_BUS, SUBORDINATE_BUS, SEC_LATENCY_TIMER
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PCI_CFG_IO_BASE = 0x1C, // IO_BASE.b, IO_LIMIT.b, SEC_STATUS.w
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PCI_CFG_MEMORY_BASE = 0x20, // MEMORY_BASE.w, MEMORY_LIMIT.w
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PCI_CFG_PREF_MEM_BASE = 0x24, // PREF_MEMORY_BASE.w, PREF_MEMORY_LIMIT.w
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PCI_CFG_PREF_BASE_UPPER32 = 0x28, // PREF_BASE_UPPER32
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PCI_CFG_PREF_LIMIT_UPPER32 = 0x2c, // PREF_LIMIT_UPPER32
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PCI_CFG_IO_BASE_UPPER16 = 0x30, // IO_BASE_UPPER16.w, IO_LIMIT_UPPER16.w
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// PCI_CFG_CAP_PTR
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PCI_CFG_BRIDGE_ROM_ADDRESS = 0x38, // BRIDGE_ROM_ADDRESS
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PCI_CFG_INTERRUPT_LINE = 0x3C, // INTERRUPT_LINE.b, INTERRUPT_PIN.b, BRIDGE_CONTROL.w
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};
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class PCIBridge : public PCIHost, public PCIDevice {
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friend class PCIHost;
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public:
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PCIBridge(std::string name);
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~PCIBridge() = default;
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// PCIHost methods
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virtual bool pci_register_mmio_region(uint32_t start_addr, uint32_t size, PCIDevice* obj);
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virtual bool pci_unregister_mmio_region(uint32_t start_addr, uint32_t size, PCIDevice* obj);
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// PCIDevice methods
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virtual uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details);
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virtual void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details);
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virtual bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res);
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virtual bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size);
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// MMIODevice methods
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virtual uint32_t read(uint32_t rgn_start, uint32_t offset, int size) {
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return 0;
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};
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virtual void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) { };
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// plugin interface for using in the derived classes
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std::function<uint8_t()> pci_rd_primary_bus;
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std::function<void(uint8_t)> pci_wr_primary_bus;
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std::function<uint8_t()> pci_rd_secondary_bus;
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std::function<void(uint8_t)> pci_wr_secondary_bus;
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std::function<uint8_t()> pci_rd_subordinate_bus;
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std::function<void(uint8_t)> pci_wr_subordinate_bus;
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std::function<uint8_t()> pci_rd_sec_latency_timer;
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std::function<void(uint8_t)> pci_wr_sec_latency_timer;
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std::function<uint16_t()> pci_rd_sec_status;
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std::function<void(uint16_t)> pci_wr_sec_status;
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std::function<uint8_t()> pci_rd_io_base;
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std::function<void(uint8_t)> pci_wr_io_base;
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std::function<uint8_t()> pci_rd_io_limit;
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std::function<void(uint8_t)> pci_wr_io_limit;
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std::function<uint16_t()> pci_rd_memory_base;
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std::function<void(uint16_t)> pci_wr_memory_base;
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std::function<uint16_t()> pci_rd_memory_limit;
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std::function<void(uint16_t)> pci_wr_memory_limit;
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std::function<uint16_t()> pci_rd_pref_mem_base;
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std::function<void(uint16_t)> pci_wr_pref_mem_base;
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std::function<uint16_t()> pci_rd_pref_mem_limit;
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std::function<void(uint16_t)> pci_wr_pref_mem_limit;
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std::function<uint32_t()> pci_rd_pref_base_upper32;
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std::function<void(uint32_t)> pci_wr_pref_base_upper32;
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std::function<uint32_t()> pci_rd_pref_limit_upper32;
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std::function<void(uint32_t)> pci_wr_pref_limit_upper32;
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std::function<uint16_t()> pci_rd_io_base_upper16;
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std::function<void(uint16_t)> pci_wr_io_base_upper16;
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std::function<uint16_t()> pci_rd_io_limit_upper16;
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std::function<void(uint16_t)> pci_wr_io_limit_upper16;
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std::function<uint16_t()> pci_rd_bridge_control;
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std::function<void(uint16_t)> pci_wr_bridge_control;
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protected:
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// PCI configuration space state
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uint8_t primary_bus = 0;
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uint8_t secondary_bus = 0;
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uint8_t subordinate_bus = 0;
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uint8_t sec_latency_timer = 0; // if supportss r/w then must reset to 0
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uint16_t sec_status = 0;
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uint8_t io_base = 0;
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uint8_t io_limit = 0;
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uint16_t memory_base = 0;
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uint16_t memory_limit = 0;
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uint16_t pref_mem_base = 0;
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uint16_t pref_mem_limit = 0;
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uint32_t pref_base_upper32 = 0;
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uint32_t pref_limit_upper32 = 0;
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uint16_t io_base_upper16 = 0;
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uint16_t io_limit_upper16 = 0;
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uint16_t bridge_control = 0;
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// 0 = not writable, 0xf8 = limits the granularity to eight PCI clocks
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uint8_t sec_latency_timer_cfg = 0;
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// 0 = not writable, 0xf0 = supports 16 bit io range, 0xf1 = supports 32 bit I/O range
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uint8_t io_cfg = 0xf0;
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// 0 = not writable, 0xfff0 = supports 32 bit memory range
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uint16_t memory_cfg = 0xfff0;
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// 0 = not writable, 0xfff0 = supports 32 bit prefetchable memory range,
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// 0xfff1 = supports 64 bit prefetchable memory range
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uint16_t pref_mem_cfg = 0xfff0;
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uint32_t io_base_32 = 0;
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uint32_t io_limit_32 = 0;
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uint64_t memory_base_32 = 0;
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uint64_t memory_limit_32 = 0;
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uint64_t pref_mem_base_64 = 0;
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uint64_t pref_mem_limit_64 = 0;
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private:
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};
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#endif /* PCI_BRIDGE_H */
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