mirror of
https://github.com/dingusdev/dingusppc.git
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136 lines
3.7 KiB
C++
136 lines
3.7 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Descriptor-based direct memory access emulation.
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Official documentation can be found in the fifth chapter of the book
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"Macintosh Technology in the Common Hardware Reference Platform"
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by Apple Computer, Inc.
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*/
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#ifndef DB_DMA_H
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#define DB_DMA_H
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#include <devices/common/dmacore.h>
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#include <devices/common/hwinterrupt.h>
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#include <cinttypes>
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#include <functional>
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/** DBDMA Channel registers offsets */
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enum DMAReg : uint32_t {
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CH_CTRL = 0,
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CH_STAT = 4,
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CMD_PTR_HI = 8,
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CMD_PTR_LO = 12,
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INT_SELECT = 16,
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BRANCH_SELECT = 20,
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WAIT_SELECT = 24,
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};
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/** Channel Status bits (DBDMA spec, 5.5.3) */
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enum : uint16_t {
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CH_STAT_ACTIVE = 0x400,
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CH_STAT_DEAD = 0x800,
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CH_STAT_WAKE = 0x1000,
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CH_STAT_FLUSH = 0x2000,
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CH_STAT_PAUSE = 0x4000,
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CH_STAT_RUN = 0x8000
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};
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/** DBDMA command (DBDMA spec, 5.6.1) - all fields are little-endian! */
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typedef struct DMACmd {
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uint16_t req_count;
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uint8_t cmd_bits;
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uint8_t cmd_key;
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uint32_t address;
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uint32_t cmd_arg;
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uint16_t res_count;
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uint16_t xfer_stat;
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} DMACmd;
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namespace DBDMA_Cmd {
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enum : uint8_t {
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OUTPUT_MORE = 0,
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OUTPUT_LAST = 1,
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INPUT_MORE = 2,
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INPUT_LAST = 3,
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STORE_QUAD = 4,
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LOAD_QUAD = 5,
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NOP = 6,
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STOP = 7
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};
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};
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typedef std::function<void(void)> DbdmaCallback;
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class DMAChannel : public DmaBidirChannel {
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public:
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DMAChannel() = default;
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~DMAChannel() = default;
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void set_callbacks(DbdmaCallback start_cb, DbdmaCallback stop_cb);
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uint32_t reg_read(uint32_t offset, int size);
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void reg_write(uint32_t offset, uint32_t value, int size);
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bool is_active();
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DmaPullResult pull_data(uint32_t req_len, uint32_t *avail_len, uint8_t **p_data);
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int push_data(const char* src_ptr, int len);
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void register_dma_int(InterruptCtrl* int_ctrl_obj, uint32_t irq_id) {
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this->int_ctrl = int_ctrl_obj;
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this->irq_id = irq_id;
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};
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protected:
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void fetch_cmd(uint32_t cmd_addr, DMACmd* p_cmd);
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uint8_t interpret_cmd(void);
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void finish_cmd();
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void xfer_quad(const DMACmd *cmd_desc, const bool is_store);
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void update_irq();
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void start(void);
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void resume(void);
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void abort(void);
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void pause(void);
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private:
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std::function<void(void)> start_cb = nullptr; // DMA channel start callback
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std::function<void(void)> stop_cb = nullptr; // DMA channel stop callback
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uint16_t ch_stat = 0;
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uint32_t cmd_ptr = 0;
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uint32_t queue_len = 0;
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uint8_t* queue_data = 0;
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uint32_t int_select = 0;
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uint32_t branch_select = 0;
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uint32_t wait_select = 0;
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bool cmd_in_progress = false;
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uint8_t cur_cmd;
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// Interrupt related stuff
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InterruptCtrl* int_ctrl = nullptr;
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uint32_t irq_id = 0;
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};
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#endif /* DB_DMA_H */
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