251 lines
9.0 KiB
C++
251 lines
9.0 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef PCI_BASE_H
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#define PCI_BASE_H
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#include <devices/common/mmiodevice.h>
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#include <devices/common/pci/pcihost.h>
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#include <cinttypes>
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#include <functional>
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#include <memory>
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#include <string>
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#include <vector>
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/** PCI configuration space header types */
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enum PCIHeaderType : uint8_t {
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PCI_HEADER_TYPE_0 = 0, // PCI Device
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PCI_HEADER_TYPE_1 = 1, // PCI-PCI Bridge
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PCI_HEADER_TYPE_2 = 2, // PCI-To-Cardbus Bridge
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};
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/** PCI configuration space registers offsets */
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enum {
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PCI_CFG_DEV_ID = 0x00, // device and vendor IDs
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PCI_CFG_STAT_CMD = 0x04, // command/status register
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PCI_CFG_CLASS_REV = 0x08, // class code and revision ID
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PCI_CFG_DWORD_3 = 0x0C, // BIST, HeaderType, Lat_Timer and Cache_Line_Size
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PCI_CFG_BAR0 = 0x10, // base address register 0 (type 0, 1, and 2)
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PCI_CFG_BAR1 = 0x14, // base address register 1 (type 0 and 1)
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PCI_CFG_DWORD_13 = 0x34, // capabilities pointer (type 0 and 1)
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PCI_CFG_DWORD_15 = 0x3C, // Max_Lat, Min_Gnt (Type 0); Bridge Control (Type 1 and 2); Int_Pin and Int_Line registers (type 0, 1, and 2)
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};
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/** PCI Vendor IDs for devices used in Power Macintosh computers. */
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enum {
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PCI_VENDOR_ATI = 0x1002,
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PCI_VENDOR_DEC = 0x1011,
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PCI_VENDOR_MOTOROLA = 0x1057,
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PCI_VENDOR_APPLE = 0x106B,
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PCI_VENDOR_NVIDIA = 0x10DE,
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};
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/** PCI BAR types */
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enum PCIBarType : uint32_t {
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Unused = 0,
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Io_16_Bit,
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Io_32_Bit,
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Mem_20_Bit, // legacy type for < 1MB memory
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Mem_32_Bit,
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Mem_64_Bit_Lo,
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Mem_64_Bit_Hi
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};
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typedef struct {
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uint32_t bar_num;
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uint32_t bar_cfg;
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} BarConfig;
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class PCIBase : public MMIODevice {
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public:
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PCIBase(std::string name, PCIHeaderType hdr_type, int num_bars);
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virtual ~PCIBase() = default;
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virtual bool supports_io_space() {
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return has_io_space;
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};
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/* I/O space access methods */
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virtual bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res) {
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return false;
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};
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virtual bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size) {
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return false;
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};
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// configuration space access methods
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virtual uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details);
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virtual void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details);
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// plugin interface for using in the derived classes
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std::function<uint16_t()> pci_rd_stat;
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std::function<void(uint16_t)> pci_wr_stat;
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std::function<uint16_t()> pci_rd_cmd;
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std::function<void(uint16_t)> pci_wr_cmd;
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std::function<uint8_t()> pci_rd_bist;
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std::function<void(uint8_t)> pci_wr_bist;
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std::function<uint8_t()> pci_rd_lat_timer;
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std::function<void(uint8_t)> pci_wr_lat_timer;
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std::function<uint8_t()> pci_rd_cache_lnsz;
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std::function<void(uint8_t)> pci_wr_cache_lnsz;
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std::function<void(int)> pci_notify_bar_change;
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int attach_exp_rom_image(const std::string img_path);
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virtual void set_host(PCIHost* host_instance) {
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this->host_instance = host_instance;
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}
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virtual void set_multi_function(bool is_multi_function) {
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this->hdr_type = is_multi_function ? (this->hdr_type | 0x80) : (this->hdr_type & 0x7f);
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}
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virtual void set_irq_pin(uint8_t irq_pin) {
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this->irq_pin = irq_pin;
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}
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virtual void pci_interrupt(uint8_t irq_line_state) {
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this->host_instance->pci_interrupt(irq_line_state, this);
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}
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// MMIODevice methods
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virtual uint32_t read(uint32_t rgn_start, uint32_t offset, int size) { return 0; }
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virtual void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) { }
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protected:
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void set_bar_value(int bar_num, uint32_t value);
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void setup_bars(std::vector<BarConfig> cfg_data);
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void finish_config_bars();
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void pci_wr_exp_rom_bar(uint32_t data);
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void map_exp_rom_mem();
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void unmap_exp_rom_mem();
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std::string pci_name; // human-readable device name
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PCIHost* host_instance; // host bridge instance to call back
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// PCI configuration space state (type 0, 1, and 2)
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command = 0;
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uint16_t status = 0;
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uint32_t class_rev; // class code and revision id
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uint8_t cache_ln_sz = 0; // cache line size
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uint8_t lat_timer = 0; // latency timer
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uint8_t hdr_type; // header type, single function
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uint8_t cap_ptr = 0; // capabilities ptr
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uint8_t irq_pin = 0;
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uint8_t irq_line = 0;
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bool has_io_space = false;
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int num_bars; // number of BARs. Type 0:6, type 1:2, type 2:1 (4K)
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uint32_t bars[6] = { 0 }; // BARs (base address registers)
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uint32_t bars_cfg[6] = { 0 }; // configuration values for BARs
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PCIBarType bars_typ[6] = { PCIBarType::Unused }; // types for BARs
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// PCI configuration space state (type 0 and 1)
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uint32_t exp_bar_cfg = 0; // expansion ROM configuration
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uint32_t exp_rom_bar = 0; // expansion ROM base address register
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uint32_t exp_rom_addr = 0; // expansion ROM base address
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uint32_t exp_rom_size = 0; // expansion ROM size in bytes
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std::unique_ptr<uint8_t[]> exp_rom_data;
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// 0 = not writable; 1 = bit is enabled in command register
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uint16_t command_cfg = 0xffff - (1<<3) - (1<<7); // disable: special cycles and stepping
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};
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inline uint32_t pci_cfg_log(uint32_t value, AccessDetails &details) {
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switch (details.size << 2 | details.offset) {
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case 0x04: return (uint8_t) value;
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case 0x05: return (uint8_t)(value >> 8);
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case 0x06: return (uint8_t)(value >> 16);
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case 0x07: return (uint8_t)(value >> 24);
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case 0x08: return (uint16_t) value;
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case 0x09: return (uint16_t) (value >> 8);
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case 0x0a: return (uint16_t) (value >> 16);
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case 0x0b: return (uint16_t)((value >> 24) | (value << 8));
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case 0x10: return value;
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case 0x11: return (value >> 8) | (value << 24);
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case 0x12: return (value >> 16) | (value << 16);
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case 0x13: return (value >> 24) | (value << 8);
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default: return 0xffffffff;
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}
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}
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#define LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER() \
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do { if ((details.flags & PCI_CONFIG_DIRECTION) == PCI_CONFIG_READ) { \
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VLOG_F( \
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(~-details.size & details.offset) ? loguru::Verbosity_ERROR : loguru::Verbosity_WARNING, \
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"%s: read unimplemented config register @%02x.%c", \
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this->name.c_str(), reg_offs + details.offset, \
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SIZE_ARG(details.size) \
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); \
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} } while(0)
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#define LOG_NAMED_CONFIG_REGISTER(reg_verb, reg_name) \
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VLOG_F( \
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(~-details.size & details.offset) ? loguru::Verbosity_ERROR : loguru::Verbosity_WARNING, \
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"%s: %s %s register @%02x.%c = %0*x", \
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this->name.c_str(), reg_verb, reg_name, reg_offs + details.offset, \
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SIZE_ARG(details.size), \
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details.size * 2, pci_cfg_log(value, details) \
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)
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#define LOG_READ_NAMED_CONFIG_REGISTER(reg_name) \
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do { if ((details.flags & PCI_CONFIG_DIRECTION) == PCI_CONFIG_READ) { \
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LOG_NAMED_CONFIG_REGISTER("read ", reg_name); \
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} } while(0)
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#define LOG_WRITE_NAMED_CONFIG_REGISTER(reg_name) \
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LOG_NAMED_CONFIG_REGISTER("write", reg_name)
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#define LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER_WITH_VALUE() \
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LOG_READ_NAMED_CONFIG_REGISTER("unimplemented config")
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#define LOG_WRITE_UNIMPLEMENTED_CONFIG_REGISTER() \
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LOG_WRITE_NAMED_CONFIG_REGISTER("unimplemented config")
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#define LOG_READ_NON_EXISTENT_PCI_DEVICE() \
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LOG_F( \
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ERROR, \
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"%s err: read attempt from non-existent PCI device %02x:%02x.%x @%02x.%c", \
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + details.offset, \
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SIZE_ARG(details.size) \
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)
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#define LOG_WRITE_NON_EXISTENT_PCI_DEVICE() \
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LOG_F( \
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ERROR, \
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"%s err: write attempt to non-existent PCI device %02x:%02x.%x @%02x.%c = %0*x", \
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + details.offset, \
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SIZE_ARG(details.size), \
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details.size * 2, BYTESWAP_SIZED(value, details.size) \
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)
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#endif /* PCI_BASE_H */
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