mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-09-01 02:29:04 +00:00
246 lines
7.6 KiB
C++
246 lines
7.6 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file MESH (Macintosh Enhanced SCSI Hardware) controller emulation. */
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#include <core/timermanager.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/scsi/mesh.h>
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#include <devices/deviceregistry.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <cinttypes>
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using namespace MeshScsi;
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int MeshController::device_postinit()
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{
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this->bus_obj = dynamic_cast<ScsiBus*>(gMachineObj->get_comp_by_name("Scsi0"));
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this->int_ctrl = dynamic_cast<InterruptCtrl*>(
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gMachineObj->get_comp_by_type(HWCompType::INT_CTRL));
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this->irq_id = this->int_ctrl->register_dev_int(IntSrc::SCSI1);
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return 0;
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}
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void MeshController::reset(bool is_hard_reset)
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{
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this->cur_cmd = SeqCmd::NoOperation;
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this->int_mask = 0;
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if (is_hard_reset) {
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this->bus_stat = 0;
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this->sync_params = 2; // guessed
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}
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}
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uint8_t MeshController::read(uint8_t reg_offset)
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{
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switch(reg_offset) {
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case MeshReg::Sequence:
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return this->cur_cmd;
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case MeshReg::BusStatus0:
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return this->bus_obj->test_ctrl_lines(0xFFU);
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case MeshReg::BusStatus1:
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return this->bus_obj->test_ctrl_lines(0xE000U) >> 8;
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case MeshReg::Exception:
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return 0;
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case MeshReg::Error:
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return 0;
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case MeshReg::IntMask:
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return this->int_mask;
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case MeshReg::Interrupt:
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return this->int_stat;
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case MeshReg::MeshID:
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return this->chip_id; // tell them who we are
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default:
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LOG_F(WARNING, "MESH: read from unimplemented register at offset 0x%x", reg_offset);
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}
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return 0;
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}
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void MeshController::write(uint8_t reg_offset, uint8_t value)
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{
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uint16_t new_stat;
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switch(reg_offset) {
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case MeshReg::Sequence:
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perform_command(value);
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break;
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case MeshReg::BusStatus1:
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new_stat = value << 8;
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if (new_stat != this->bus_stat) {
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for (uint16_t mask = SCSI_CTRL_RST; mask >= SCSI_CTRL_SEL; mask >>= 1) {
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if ((new_stat ^ this->bus_stat) & mask) {
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if (new_stat & mask)
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this->bus_obj->assert_ctrl_line(new_stat, mask);
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else
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this->bus_obj->release_ctrl_line(new_stat, mask);
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}
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}
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this->bus_stat = new_stat;
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}
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break;
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case MeshReg::IntMask:
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this->int_mask = value;
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break;
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case MeshReg::Interrupt:
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this->int_stat &= ~(value & INT_MASK); // clear requested interrupt bits
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update_irq();
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break;
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case MeshReg::SourceID:
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this->src_id = value;
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break;
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case MeshReg::DestID:
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this->dst_id = value;
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break;
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case MeshReg::SyncParms:
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this->sync_params = value;
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break;
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case MeshReg::SelTimeOut:
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LOG_F(9, "MESH: selection timeout set to 0x%x", value);
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break;
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default:
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LOG_F(WARNING, "MESH: write to unimplemented register at offset 0x%x",
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reg_offset);
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}
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}
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void MeshController::perform_command(const uint8_t cmd)
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{
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this->cur_cmd = cmd;
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this->int_stat &= ~INT_CMD_DONE;
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switch (this->cur_cmd & 0xF) {
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case SeqCmd::Arbitrate:
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this->cur_state = SeqState::BUS_FREE;
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this->sequencer();
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break;
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case SeqCmd::Select:
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this->cur_state = SeqState::SEL_BEGIN;
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this->sequencer();
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break;
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case SeqCmd::DisReselect:
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LOG_F(INFO, "MESH: DisReselect command requested");
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break;
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case SeqCmd::ResetMesh:
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this->reset(false);
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this->int_stat |= INT_CMD_DONE;
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break;
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case SeqCmd::FlushFIFO:
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LOG_F(INFO, "MESH: FlushFIFO command requested");
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break;
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default:
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LOG_F(ERROR, "MESH: unsupported sequencer command 0x%X", this->cur_cmd);
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}
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}
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void MeshController::seq_defer_state(uint64_t delay_ns)
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{
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seq_timer_id = TimerManager::get_instance()->add_oneshot_timer(
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delay_ns,
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[this]() {
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// re-enter the sequencer with the state specified in next_state
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this->cur_state = this->next_state;
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this->sequencer();
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});
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}
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void MeshController::sequencer()
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{
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switch (this->cur_state) {
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case SeqState::IDLE:
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break;
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case SeqState::BUS_FREE:
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if (this->bus_obj->current_phase() == ScsiPhase::BUS_FREE) {
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this->next_state = SeqState::ARB_BEGIN;
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this->seq_defer_state(BUS_FREE_DELAY + BUS_SETTLE_DELAY);
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} else { // continue waiting
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_FREE_DELAY);
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}
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break;
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case SeqState::ARB_BEGIN:
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if (!this->bus_obj->begin_arbitration(this->src_id)) {
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LOG_F(ERROR, "MESH: arbitration error, bus not free!");
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this->bus_obj->release_ctrl_lines(this->src_id);
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_CLEAR_DELAY);
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break;
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}
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this->next_state = SeqState::ARB_END;
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this->seq_defer_state(ARB_DELAY);
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break;
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case SeqState::ARB_END:
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if (this->bus_obj->end_arbitration(this->src_id) &&
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!this->bus_obj->test_ctrl_lines(SCSI_CTRL_SEL)) { // arbitration won
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this->bus_obj->assert_ctrl_line(this->src_id, SCSI_CTRL_SEL);
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} else { // arbitration lost
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LOG_F(INFO, "MESH: arbitration lost!");
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this->bus_obj->release_ctrl_lines(this->src_id);
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this->exception |= EXC_ARB_LOST;
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this->int_stat |= INT_EXCEPTION;
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}
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this->int_stat |= INT_CMD_DONE;
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update_irq();
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break;
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case SeqState::SEL_BEGIN:
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this->bus_obj->begin_selection(this->src_id, this->dst_id, this->cur_cmd & 0x20);
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this->next_state = SeqState::SEL_END;
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this->seq_defer_state(SEL_TIME_OUT);
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break;
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case SeqState::SEL_END:
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if (this->bus_obj->end_selection(this->src_id, this->dst_id)) {
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this->bus_obj->release_ctrl_line(this->src_id, SCSI_CTRL_SEL);
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LOG_F(9, "MESH: selection completed");
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} else { // selection timeout
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this->bus_obj->disconnect(this->src_id);
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this->cur_state = SeqState::IDLE;
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this->exception |= EXC_SEL_TIMEOUT;
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this->int_stat |= INT_EXCEPTION;
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}
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this->int_stat |= INT_CMD_DONE;
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update_irq();
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break;
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default:
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ABORT_F("MESH: unimplemented sequencer state %d", this->cur_state);
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}
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}
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void MeshController::update_irq()
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{
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uint8_t new_irq = !!(this->int_stat & this->int_mask);
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if (new_irq != this->irq) {
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this->irq = new_irq;
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this->int_ctrl->ack_int(this->irq_id, new_irq);
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}
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}
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static const DeviceDescription Mesh_Descriptor = {
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MeshController::create, {}, {}
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};
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REGISTER_DEVICE(Mesh, Mesh_Descriptor);
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