mirror of
https://github.com/dingusdev/dingusppc.git
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661 lines
22 KiB
C++
661 lines
22 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file NCR53C94/Am53CF94 SCSI controller emulation. */
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#include <core/timermanager.h>
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#include <devices/common/hwcomponent.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/scsi/sc53c94.h>
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#include <devices/deviceregistry.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <cinttypes>
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#include <cstring>
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Sc53C94::Sc53C94(uint8_t chip_id, uint8_t my_id) : ScsiDevice(my_id)
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{
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this->chip_id = chip_id;
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this->my_bus_id = my_id;
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supports_types(HWCompType::SCSI_HOST | HWCompType::SCSI_DEV);
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reset_device();
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}
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int Sc53C94::device_postinit()
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{
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this->bus_obj = dynamic_cast<ScsiBus*>(gMachineObj->get_comp_by_name("Scsi0"));
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this->bus_obj->register_device(7, static_cast<ScsiDevice*>(this));
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this->int_ctrl = dynamic_cast<InterruptCtrl*>(
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gMachineObj->get_comp_by_type(HWCompType::INT_CTRL));
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this->irq_id = this->int_ctrl->register_dev_int(IntSrc::SCSI1);
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return 0;
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}
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void Sc53C94::reset_device()
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{
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// part-unique ID to be read using a magic sequence
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this->set_xfer_count = this->chip_id << 16;
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this->clk_factor = 2;
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this->sel_timeout = 0;
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this->is_initiator = true;
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// clear command FIFO
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this->cmd_fifo_pos = 0;
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// clear data FIFO
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this->data_fifo_pos = 0;
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this->data_fifo[0] = 0;
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this->seq_step = 0;
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this->status = 0;
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}
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uint8_t Sc53C94::read(uint8_t reg_offset)
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{
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uint8_t status, int_status;
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switch (reg_offset) {
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case Read::Reg53C94::Xfer_Cnt_LSB:
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return this->xfer_count & 0xFFU;
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case Read::Reg53C94::Xfer_Cnt_MSB:
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return (this->xfer_count >> 8) & 0xFFU;
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case Read::Reg53C94::FIFO:
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return this->fifo_pop();
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case Read::Reg53C94::Command:
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return this->cmd_fifo[0];
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case Read::Reg53C94::Status:
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status = bus_obj->test_ctrl_lines(SCSI_CTRL_MSG | SCSI_CTRL_CD | SCSI_CTRL_IO);
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return (this->status & 0xF8) | status;
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case Read::Reg53C94::Int_Status:
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int_status = this->int_status;
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this->seq_step = 0;
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this->int_status = 0;
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this->update_irq();
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return int_status;
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case Read::Reg53C94::Seq_Step:
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return this->seq_step;
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case Read::Reg53C94::FIFO_Flags:
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return (this->seq_step << 5) | (this->data_fifo_pos & 0x1F);
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case Read::Reg53C94::Config_1:
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return this->config1;
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case Read::Reg53C94::Config_3:
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return this->config3;
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case Read::Reg53C94::Xfer_Cnt_Hi:
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if (this->config2 & CFG2_ENF) {
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return (this->xfer_count >> 16) & 0xFFU;
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}
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break;
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default:
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LOG_F(INFO, "SC53C94: reading from register %d", reg_offset);
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}
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return 0;
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}
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void Sc53C94::write(uint8_t reg_offset, uint8_t value)
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{
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switch (reg_offset) {
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case Write::Reg53C94::Xfer_Cnt_LSB:
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this->set_xfer_count = (this->set_xfer_count & ~0xFFU) | value;
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break;
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case Write::Reg53C94::Xfer_Cnt_MSB:
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this->set_xfer_count = (this->set_xfer_count & ~0xFF00U) | (value << 8);
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break;
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case Write::Reg53C94::Command:
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update_command_reg(value);
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break;
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case Write::Reg53C94::FIFO:
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fifo_push(value);
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break;
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case Write::Reg53C94::Dest_Bus_ID:
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this->target_id = value & 7;
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break;
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case Write::Reg53C94::Sel_Timeout:
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this->sel_timeout = value;
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break;
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case Write::Reg53C94::Sync_Offset:
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this->sync_offset = value;
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break;
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case Write::Reg53C94::Clock_Factor:
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this->clk_factor = value;
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break;
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case Write::Reg53C94::Config_1:
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if ((value & 7) != this->my_bus_id) {
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ABORT_F("SC53C94: HBA bus ID mismatch!");
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}
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this->config1 = value;
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break;
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case Write::Reg53C94::Config_2:
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this->config2 = value;
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break;
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case Write::Reg53C94::Config_3:
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this->config3 = value;
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break;
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default:
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LOG_F(INFO, "SC53C94: writing 0x%X to %d register", value, reg_offset);
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}
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}
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uint16_t Sc53C94::pseudo_dma_read()
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{
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uint16_t data_word;
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bool is_done = false;
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if (this->data_fifo_pos >= 2) {
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// remove one word from FIFO
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data_word = (this->data_fifo[0] << 8) | this->data_fifo[1];
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this->data_fifo_pos -= 2;
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std:memmove(this->data_fifo, &this->data_fifo[2], this->data_fifo_pos);
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// update DMA status
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if ((this->cmd_fifo[0] & 0x80)) {
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this->xfer_count -= 2;
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if (!this->xfer_count) {
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is_done = true;
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this->status |= STAT_TC; // signal zero transfer count
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this->cur_state = SeqState::XFER_END;
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this->sequencer();
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}
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}
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}
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// see if we need to refill FIFO
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if (!this->data_fifo_pos && !is_done) {
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this->sequencer();
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}
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return data_word;
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}
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void Sc53C94::update_command_reg(uint8_t cmd)
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{
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if (this->on_reset && (cmd & 0x7F) != CMD_NOP) {
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LOG_F(WARNING, "SC53C94: command register blocked after RESET!");
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return;
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}
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// NOTE: Reset Device (chip), Reset Bus and DMA Stop commands execute
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// immediately while all others are placed into the command FIFO
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switch (cmd & 0x7F) {
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case CMD_RESET_DEVICE:
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case CMD_RESET_BUS:
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case CMD_DMA_STOP:
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this->cmd_fifo_pos = 0; // put them at the bottom of the command FIFO
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}
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if (this->cmd_fifo_pos < 2) {
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// put new command into the command FIFO
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this->cmd_fifo[this->cmd_fifo_pos++] = cmd;
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if (this->cmd_fifo_pos == 1) {
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exec_command();
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}
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} else {
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LOG_F(ERROR, "SC53C94: the top of the command FIFO overwritten!");
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this->status |= STAT_GE; // signal IOE/Gross Error
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}
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}
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void Sc53C94::exec_command()
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{
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uint8_t cmd = this->cur_cmd = this->cmd_fifo[0] & 0x7F;
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bool is_dma_cmd = !!(this->cmd_fifo[0] & 0x80);
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if (is_dma_cmd) {
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if (this->config2 & CFG2_ENF) { // extended mode: 24-bit
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this->xfer_count = this->set_xfer_count & 0xFFFFFFUL;
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} else { // standard mode: 16-bit
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this->xfer_count = this->set_xfer_count & 0xFFFFUL;
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if (!this->xfer_count) {
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this->xfer_count = 65536;
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}
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}
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}
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// simple commands will be executed immediately
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// complex commands will be broken into multiple steps
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// and handled by the sequencer
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switch (cmd) {
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case CMD_NOP:
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this->on_reset = false; // unblock the command register
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exec_next_command();
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break;
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case CMD_CLEAR_FIFO:
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this->data_fifo_pos = 0; // set the bottom of the data FIFO to zero
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this->data_fifo[0] = 0;
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exec_next_command();
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break;
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case CMD_RESET_DEVICE:
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reset_device();
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this->on_reset = true; // block the command register
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return;
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case CMD_RESET_BUS:
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LOG_F(INFO, "SC53C94: resetting SCSI bus...");
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// assert RST line
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this->bus_obj->assert_ctrl_line(this->my_bus_id, SCSI_CTRL_RST);
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// release RST line after 25 us
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my_timer_id = TimerManager::get_instance()->add_oneshot_timer(
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USECS_TO_NSECS(25),
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[this]() {
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this->bus_obj->release_ctrl_line(this->my_bus_id, SCSI_CTRL_RST);
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});
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if (!(config1 & 0x40)) {
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LOG_F(INFO, "SC53C94: reset interrupt issued");
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this->int_status |= INTSTAT_SRST;
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}
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exec_next_command();
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break;
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case CMD_XFER:
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if (!this->is_initiator) {
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// clear command FIFO
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this->cmd_fifo_pos = 0;
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this->int_status |= INTSTAT_ICMD;
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this->update_irq();
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} else {
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this->seq_step = 0;
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this->cmd_steps = nullptr;
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this->cur_state = SeqState::XFER_BEGIN;
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this->sequencer();
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}
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break;
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case CMD_COMPLETE_STEPS:
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static SeqDesc * complete_steps_desc = new SeqDesc[3]{
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{SeqState::RCV_STATUS, 0, 0},
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{SeqState::RCV_MESSAGE, 0, 0},
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{SeqState::CMD_COMPLETE, 0, INTSTAT_SR}
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};
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if (this->bus_obj->current_phase() != ScsiPhase::STATUS) {
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ABORT_F("Sc53C94: complete steps only works in the STATUS phase");
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}
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this->seq_step = 0;
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this->cmd_steps = complete_steps_desc;
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this->cur_state = this->cmd_steps->next_step;
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this->sequencer();
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break;
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case CMD_MSG_ACCEPTED:
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if (this->is_initiator) {
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this->bus_obj->target_next_step();
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}
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this->bus_obj->release_ctrl_line(this->my_bus_id, SCSI_CTRL_ACK);
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this->int_status |= INTSTAT_SR;
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this->int_status |= INTSTAT_DIS; // TODO: handle target disconnection properly
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this->update_irq();
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exec_next_command();
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break;
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case CMD_SELECT_NO_ATN:
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static SeqDesc * sel_no_atn_desc = new SeqDesc[3]{
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{SeqState::SEL_BEGIN, 0, INTSTAT_DIS },
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{SeqState::SEND_CMD, 3, INTSTAT_SR | INTSTAT_SO},
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{SeqState::CMD_COMPLETE, 4, INTSTAT_SR | INTSTAT_SO},
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};
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this->seq_step = 0;
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this->cmd_steps = sel_no_atn_desc;
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this->cur_state = SeqState::BUS_FREE;
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this->sequencer();
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LOG_F(9, "SC53C94: SELECT W/O ATN command started");
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break;
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case CMD_SELECT_WITH_ATN:
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static SeqDesc * sel_with_atn_desc = new SeqDesc[4]{
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{SeqState::SEL_BEGIN, 0, INTSTAT_DIS },
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{SeqState::SEND_MSG, 2, INTSTAT_SR | INTSTAT_SO},
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{SeqState::SEND_CMD, 3, INTSTAT_SR | INTSTAT_SO},
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{SeqState::CMD_COMPLETE, 4, INTSTAT_SR | INTSTAT_SO},
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};
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this->seq_step = 0;
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this->bytes_out = 1; // set message length
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this->cmd_steps = sel_with_atn_desc;
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this->cur_state = SeqState::BUS_FREE;
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this->sequencer();
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LOG_F(9, "SC53C94: SELECT WITH ATN command started");
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break;
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case CMD_ENA_SEL_RESEL:
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exec_next_command();
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break;
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default:
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LOG_F(ERROR, "SC53C94: invalid/unimplemented command 0x%X", cmd);
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this->cmd_fifo_pos--; // remove invalid command from FIFO
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this->int_status |= INTSTAT_ICMD;
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this->update_irq();
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}
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}
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void Sc53C94::exec_next_command()
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{
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if (this->cmd_fifo_pos) { // skip empty command FIFO
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this->cmd_fifo_pos--; // remove completed command
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if (this->cmd_fifo_pos) { // is there another command in the FIFO?
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this->cmd_fifo[0] = this->cmd_fifo[1]; // top -> bottom
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exec_command(); // execute it
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}
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}
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}
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void Sc53C94::fifo_push(const uint8_t data)
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{
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if (this->data_fifo_pos < DATA_FIFO_MAX) {
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this->data_fifo[this->data_fifo_pos++] = data;
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} else {
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LOG_F(ERROR, "SC53C94: data FIFO overflow!");
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this->status |= STAT_GE; // signal IOE/Gross Error
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}
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}
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uint8_t Sc53C94::fifo_pop()
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{
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uint8_t data = 0;
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if (this->data_fifo_pos < 1) {
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LOG_F(ERROR, "SC53C94: data FIFO underflow!");
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this->status |= STAT_GE; // signal IOE/Gross Error
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} else {
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data = this->data_fifo[0];
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this->data_fifo_pos--;
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std:memmove(this->data_fifo, &this->data_fifo[1], this->data_fifo_pos);
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}
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return data;
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}
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void Sc53C94::seq_defer_state(uint64_t delay_ns)
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{
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seq_timer_id = TimerManager::get_instance()->add_oneshot_timer(
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delay_ns,
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[this]() {
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// re-enter the sequencer with the state specified in next_state
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this->cur_state = this->next_state;
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this->sequencer();
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});
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}
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void Sc53C94::sequencer()
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{
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switch (this->cur_state) {
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case SeqState::IDLE:
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break;
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case SeqState::BUS_FREE:
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if (this->bus_obj->current_phase() == ScsiPhase::BUS_FREE) {
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this->next_state = SeqState::ARB_BEGIN;
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this->seq_defer_state(BUS_FREE_DELAY + BUS_SETTLE_DELAY);
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} else { // continue waiting
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_FREE_DELAY);
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}
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break;
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case SeqState::ARB_BEGIN:
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if (!this->bus_obj->begin_arbitration(this->my_bus_id)) {
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LOG_F(ERROR, "SC53C94: arbitration error, bus not free!");
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this->bus_obj->release_ctrl_lines(this->my_bus_id);
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_CLEAR_DELAY);
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break;
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}
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this->next_state = SeqState::ARB_END;
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this->seq_defer_state(ARB_DELAY);
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break;
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case SeqState::ARB_END:
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if (this->bus_obj->end_arbitration(this->my_bus_id)) { // arbitration won
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this->next_state = this->cmd_steps->next_step;
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this->seq_defer_state(BUS_CLEAR_DELAY + BUS_SETTLE_DELAY);
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} else { // arbitration lost
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LOG_F(INFO, "SC53C94: arbitration lost!");
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this->bus_obj->release_ctrl_lines(this->my_bus_id);
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_CLEAR_DELAY);
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}
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break;
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case SeqState::SEL_BEGIN:
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this->is_initiator = true;
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this->bus_obj->begin_selection(this->my_bus_id, this->target_id,
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this->cur_cmd != CMD_SELECT_NO_ATN);
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this->next_state = SeqState::SEL_END;
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this->seq_defer_state(SEL_TIME_OUT);
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break;
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case SeqState::SEL_END:
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if (this->bus_obj->end_selection(this->my_bus_id, this->target_id)) {
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this->bus_obj->release_ctrl_line(this->my_bus_id, SCSI_CTRL_SEL);
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LOG_F(9, "SC53C94: selection completed");
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} else { // selection timeout
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this->seq_step = this->cmd_steps->step_num;
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this->int_status |= this->cmd_steps->status;
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this->bus_obj->disconnect(this->my_bus_id);
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this->cur_state = SeqState::IDLE;
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this->update_irq();
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exec_next_command();
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}
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break;
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case SeqState::SEND_MSG:
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this->bus_obj->negotiate_xfer(this->data_fifo_pos, this->bytes_out);
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this->bus_obj->push_data(this->target_id, this->data_fifo, this->bytes_out);
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this->data_fifo_pos -= this->bytes_out;
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if (this->data_fifo_pos > 0) {
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std::memmove(this->data_fifo, &this->data_fifo[this->bytes_out], this->data_fifo_pos);
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}
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this->bus_obj->release_ctrl_line(this->my_bus_id, SCSI_CTRL_ATN);
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break;
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case SeqState::SEND_CMD:
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this->bus_obj->negotiate_xfer(this->data_fifo_pos, this->bytes_out);
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this->bus_obj->push_data(this->target_id, this->data_fifo, this->data_fifo_pos);
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this->data_fifo_pos = 0;
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break;
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case SeqState::CMD_COMPLETE:
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|
this->seq_step = this->cmd_steps->step_num;
|
|
this->int_status |= this->cmd_steps->status;
|
|
this->update_irq();
|
|
exec_next_command();
|
|
break;
|
|
case SeqState::XFER_BEGIN:
|
|
this->cur_bus_phase = this->bus_obj->current_phase();
|
|
switch (this->cur_bus_phase) {
|
|
case ScsiPhase::DATA_OUT:
|
|
if (this->cmd_fifo[0] & 0x80) {
|
|
this->cur_state = SeqState::SEND_DATA;
|
|
break;
|
|
}
|
|
this->bus_obj->push_data(this->target_id, this->data_fifo, this->data_fifo_pos);
|
|
this->data_fifo_pos = 0;
|
|
this->cur_state = SeqState::XFER_END;
|
|
this->sequencer();
|
|
break;
|
|
case ScsiPhase::DATA_IN:
|
|
this->bus_obj->negotiate_xfer(this->data_fifo_pos, this->bytes_out);
|
|
this->cur_state = SeqState::RCV_DATA;
|
|
this->rcv_data();
|
|
if (!(this->cmd_fifo[0] & 0x80)) {
|
|
this->cur_state = SeqState::XFER_END;
|
|
this->sequencer();
|
|
}
|
|
}
|
|
break;
|
|
case SeqState::XFER_END:
|
|
if (this->is_initiator) {
|
|
this->bus_obj->target_next_step();
|
|
}
|
|
this->int_status |= INTSTAT_SR;
|
|
this->update_irq();
|
|
exec_next_command();
|
|
break;
|
|
case SeqState::SEND_DATA:
|
|
break;
|
|
case SeqState::RCV_DATA:
|
|
// check for unexpected bus phase changes
|
|
if (this->bus_obj->current_phase() != this->cur_bus_phase) {
|
|
this->cmd_fifo_pos = 0; // clear command FIFO
|
|
this->int_status |= INTSTAT_SR;
|
|
this->update_irq();
|
|
} else {
|
|
this->rcv_data();
|
|
}
|
|
break;
|
|
case SeqState::RCV_STATUS:
|
|
case SeqState::RCV_MESSAGE:
|
|
this->bus_obj->negotiate_xfer(this->data_fifo_pos, this->bytes_out);
|
|
this->rcv_data();
|
|
if (this->is_initiator) {
|
|
if (this->cur_state == SeqState::RCV_STATUS) {
|
|
this->bus_obj->target_next_step();
|
|
} else if (this->cur_state == SeqState::RCV_MESSAGE) {
|
|
this->bus_obj->assert_ctrl_line(this->my_bus_id, SCSI_CTRL_ACK);
|
|
this->cmd_steps++;
|
|
this->cur_state = this->cmd_steps->next_step;
|
|
this->sequencer();
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
ABORT_F("SC53C94: unimplemented sequencer state %d", this->cur_state);
|
|
}
|
|
}
|
|
|
|
void Sc53C94::update_irq()
|
|
{
|
|
uint8_t new_irq = !!(this->int_status != 0);
|
|
if (new_irq != this->irq) {
|
|
this->irq = new_irq;
|
|
this->status = (this->status & 0x7F) | (new_irq << 7);
|
|
this->int_ctrl->ack_int(this->irq_id, new_irq);
|
|
}
|
|
}
|
|
|
|
void Sc53C94::notify(ScsiBus* bus_obj, ScsiMsg msg_type, int param)
|
|
{
|
|
switch (msg_type) {
|
|
case ScsiMsg::CONFIRM_SEL:
|
|
if (this->target_id == param) {
|
|
// cancel selection timeout timer
|
|
TimerManager::get_instance()->cancel_timer(this->seq_timer_id);
|
|
this->cur_state = SeqState::SEL_END;
|
|
this->sequencer();
|
|
} else {
|
|
LOG_F(WARNING, "SC53C94: ignore invalid selection confirmation message");
|
|
}
|
|
break;
|
|
case ScsiMsg::BUS_PHASE_CHANGE:
|
|
if (param != ScsiPhase::BUS_FREE && this->cmd_steps != nullptr) {
|
|
this->cmd_steps++;
|
|
this->cur_state = this->cmd_steps->next_step;
|
|
this->sequencer();
|
|
}
|
|
break;
|
|
default:
|
|
LOG_F(9, "SC53C94: ignore notification message, type: %d", msg_type);
|
|
}
|
|
}
|
|
|
|
int Sc53C94::send_data(uint8_t* dst_ptr, int count)
|
|
{
|
|
if (dst_ptr == nullptr || !count) {
|
|
return 0;
|
|
}
|
|
|
|
int actual_count = std::min(this->data_fifo_pos, count);
|
|
|
|
// move data out of the data FIFO
|
|
std::memcpy(dst_ptr, this->data_fifo, actual_count);
|
|
|
|
// remove the just readed data from the data FIFO
|
|
this->data_fifo_pos -= actual_count;
|
|
if (this->data_fifo_pos > 0) {
|
|
std::memmove(this->data_fifo, &this->data_fifo[actual_count], this->data_fifo_pos);
|
|
} else {
|
|
this->cmd_steps++;
|
|
this->cur_state = this->cmd_steps->next_step;
|
|
this->sequencer();
|
|
}
|
|
|
|
return actual_count;
|
|
}
|
|
|
|
bool Sc53C94::rcv_data()
|
|
{
|
|
int req_count;
|
|
|
|
// return if REQ line is negated
|
|
if (!this->bus_obj->test_ctrl_lines(SCSI_CTRL_REQ)) {
|
|
return false;
|
|
}
|
|
|
|
if ((this->cmd_fifo[0] & 0x80) && this->cur_bus_phase == ScsiPhase::DATA_IN) {
|
|
req_count = std::min((int)this->xfer_count, DATA_FIFO_MAX - this->data_fifo_pos);
|
|
} else {
|
|
req_count = 1;
|
|
}
|
|
|
|
this->bus_obj->pull_data(this->target_id, &this->data_fifo[this->data_fifo_pos], req_count);
|
|
this->data_fifo_pos += req_count;
|
|
return true;
|
|
}
|
|
|
|
void Sc53C94::real_dma_xfer(int direction)
|
|
{
|
|
bool is_done = false;
|
|
|
|
if (direction) {
|
|
uint32_t got_bytes;
|
|
uint8_t* src_ptr;
|
|
|
|
while (this->xfer_count) {
|
|
this->dma_ch->pull_data(std::min((int)this->xfer_count, DATA_FIFO_MAX),
|
|
&got_bytes, &src_ptr);
|
|
std::memcpy(this->data_fifo, src_ptr, got_bytes);
|
|
this->data_fifo_pos = got_bytes;
|
|
this->bus_obj->push_data(this->target_id, this->data_fifo, this->data_fifo_pos);
|
|
|
|
this->xfer_count -= this->data_fifo_pos;
|
|
this->data_fifo_pos = 0;
|
|
if (!this->xfer_count) {
|
|
is_done = true;
|
|
this->status |= STAT_TC; // signal zero transfer count
|
|
this->cur_state = SeqState::XFER_END;
|
|
this->sequencer();
|
|
}
|
|
}
|
|
} else { // transfer data from target to host's memory
|
|
while (this->xfer_count) {
|
|
if (this->data_fifo_pos) {
|
|
this->dma_ch->push_data((char*)this->data_fifo, this->data_fifo_pos);
|
|
|
|
this->xfer_count -= this->data_fifo_pos;
|
|
this->data_fifo_pos = 0;
|
|
if (!this->xfer_count) {
|
|
is_done = true;
|
|
this->status |= STAT_TC; // signal zero transfer count
|
|
this->cur_state = SeqState::XFER_END;
|
|
this->sequencer();
|
|
}
|
|
}
|
|
|
|
// see if we need to refill FIFO
|
|
if (!this->data_fifo_pos && !is_done) {
|
|
this->sequencer();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static const DeviceDescription Sc53C94_Descriptor = {
|
|
Sc53C94::create, {}, {}
|
|
};
|
|
|
|
REGISTER_DEVICE(Sc53C94, Sc53C94_Descriptor);
|