mirror of
https://github.com/dingusdev/dingusppc.git
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Result of running IWYU (https://include-what-you-use.org/) and applying most of the suggestions about unncessary includes and forward declarations. Was motivated by observing that <thread> was being included in ppcopcodes.cpp even though it was unused (found while researching the use of threads), but seems generally good to help with build times and correctness.
238 lines
6.0 KiB
C++
238 lines
6.0 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file NCR53C94/Am53CF94 SCSI controller definitions. */
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/* NOTE: Power Macintosh computers don't have a real NCR 53C94 chip.
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The corresponding functionality is provided by the 53CF94 compatible
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cell in the custom Curio IC (Am79C950).
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*/
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#ifndef SC_53C94_H
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#define SC_53C94_H
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#include <devices/common/scsi/scsi.h>
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#include <cinttypes>
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#include <memory>
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class DmaBidirChannel;
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class InterruptCtrl;
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#define DATA_FIFO_MAX 16
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/** 53C94 read registers */
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namespace Read {
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enum Reg53C94 : uint8_t {
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Xfer_Cnt_LSB = 0,
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Xfer_Cnt_MSB = 1,
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FIFO = 2,
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Command = 3,
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Status = 4,
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Int_Status = 5,
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Seq_Step = 6,
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FIFO_Flags = 7,
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Config_1 = 8,
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Config_2 = 0xB,
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Config_3 = 0xC,
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Config_4 = 0xD, // Am53CF94 extension
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Xfer_Cnt_Hi = 0xE, // Am53CF94 extension
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};
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};
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/** 53C94 write registers */
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namespace Write {
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enum Reg53C94 : uint8_t {
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Xfer_Cnt_LSB = 0,
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Xfer_Cnt_MSB = 1,
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FIFO = 2,
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Command = 3,
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Dest_Bus_ID = 4,
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Sel_Timeout = 5,
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Sync_Period = 6,
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Sync_Offset = 7,
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Config_1 = 8,
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Clock_Factor = 9,
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Test_Mode = 0xA,
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Config_2 = 0xB,
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Config_3 = 0xC,
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Config_4 = 0xD, // Am53CF94 extension
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Xfer_Cnt_Hi = 0xE, // Am53CF94 extension
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Data_Align = 0xF
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};
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};
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/** NCR53C94/Am53CF94 commands. */
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enum {
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CMD_NOP = 0,
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CMD_CLEAR_FIFO = 1,
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CMD_RESET_DEVICE = 2,
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CMD_RESET_BUS = 3,
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CMD_DMA_STOP = 4,
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CMD_XFER = 0x10,
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CMD_COMPLETE_STEPS = 0x11,
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CMD_MSG_ACCEPTED = 0x12,
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CMD_SELECT_NO_ATN = 0x41,
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CMD_SELECT_WITH_ATN = 0x42,
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CMD_ENA_SEL_RESEL = 0x44,
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};
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/** Status register bits. **/
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enum {
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STAT_TC = 1 << 4, // Terminal count (NCR) / count to zero (AMD)
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STAT_GE = 1 << 6, // Gross Error (NCR) / Illegal Operation Error (AMD)
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};
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/** Interrupt status register bits. */
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enum {
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INTSTAT_SRST = 0x80, // bus reset
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INTSTAT_ICMD = 0x40, // invalid command
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INTSTAT_DIS = 0x20, // disconnected
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INTSTAT_SR = 0x10, // service request
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INTSTAT_SO = 0x08, // successful operation
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INTSTAT_RESEL = 0x04, // reselected
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INTSTAT_SELA = 0x02, // selected as a target with attention
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INTSTAT_SEL = 0x01, // selected as a target without attention
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};
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enum {
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CFG2_ENF = 0x40, // Am53CF94: enable features (ENF) bit
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};
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/** Sequencer states. */
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namespace SeqState {
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enum {
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IDLE = 0,
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BUS_FREE,
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ARB_BEGIN,
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ARB_END,
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SEL_BEGIN,
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SEL_END,
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SEND_MSG,
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SEND_CMD,
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CMD_COMPLETE,
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XFER_BEGIN,
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XFER_END,
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SEND_DATA,
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RCV_DATA,
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RCV_STATUS,
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RCV_MESSAGE,
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};
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};
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/** Sequence descriptor for sequencer commands. */
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typedef struct {
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int next_step;
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int step_num;
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int status;
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} SeqDesc;
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class Sc53C94 : public ScsiDevice {
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public:
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Sc53C94(uint8_t chip_id=12, uint8_t my_id=7);
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~Sc53C94() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<Sc53C94>(new Sc53C94());
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}
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// HWComponent methods
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int device_postinit();
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// 53C94 registers access
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uint8_t read(uint8_t reg_offset);
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void write(uint8_t reg_offset, uint8_t value);
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uint16_t pseudo_dma_read();
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// real DMA control
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void real_dma_xfer(int direction);
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void set_dma_channel(DmaBidirChannel *dma_ch) {
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this->dma_ch = dma_ch;
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};
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// ScsiDevice methods
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void notify(ScsiBus* bus_obj, ScsiMsg msg_type, int param);
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bool prepare_data() { return false; };
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bool has_data() { return this->data_fifo_pos != 0; };
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int send_data(uint8_t* dst_ptr, int count);
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void process_command() {};
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protected:
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void reset_device();
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void update_command_reg(uint8_t cmd);
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void exec_command();
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void exec_next_command();
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void fifo_push(const uint8_t data);
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uint8_t fifo_pop();
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void sequencer();
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void seq_defer_state(uint64_t delay_ns);
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bool rcv_data();
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void update_irq();
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private:
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uint8_t chip_id;
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uint8_t my_bus_id;
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ScsiBus* bus_obj;
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uint32_t my_timer_id;
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uint8_t cmd_fifo[2];
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uint8_t data_fifo[16];
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int cmd_fifo_pos;
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int data_fifo_pos;
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int bytes_out;
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bool on_reset = false;
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uint32_t xfer_count;
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uint32_t set_xfer_count;
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uint8_t status;
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uint8_t target_id;
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uint8_t int_status;
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uint8_t seq_step;
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uint8_t sel_timeout;
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uint8_t sync_offset;
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uint8_t clk_factor;
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uint8_t config1;
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uint8_t config2;
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uint8_t config3;
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// sequencer state
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uint32_t seq_timer_id;
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uint32_t cur_state;
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uint32_t next_state;
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SeqDesc* cmd_steps;
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bool is_initiator;
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uint8_t cur_cmd;
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int cur_bus_phase;
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// interrupt related stuff
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InterruptCtrl* int_ctrl = nullptr;
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uint32_t irq_id = 0;
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uint8_t irq = 0;
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// DMA related stuff
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DmaBidirChannel* dma_ch;
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};
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#endif // SC_53C94_H
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