mirror of
https://github.com/dingusdev/dingusppc.git
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Result of running IWYU (https://include-what-you-use.org/) and applying most of the suggestions about unncessary includes and forward declarations. Was motivated by observing that <thread> was being included in ppcopcodes.cpp even though it was unused (found while researching the use of threads), but seems generally good to help with build times and correctness.
229 lines
9.5 KiB
C++
229 lines
9.5 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <devices/common/pci/pcibridge.h>
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#include <devices/common/pci/pcidevice.h>
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#include <devices/common/pci/pcihost.h>
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#include <loguru.hpp>
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PCIBridge::PCIBridge(std::string name) : PCIDevice(name)
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{
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this->num_bars = 2;
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this->hdr_type = 1;
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this->pci_rd_primary_bus = [this]() { return this->primary_bus; };
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this->pci_rd_secondary_bus = [this]() { return this->secondary_bus; };
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this->pci_rd_subordinate_bus = [this]() { return this->subordinate_bus; };
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this->pci_rd_sec_latency_timer = [this]() { return this->sec_latency_timer; };
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this->pci_rd_sec_status = [this]() { return this->sec_status; };
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this->pci_rd_memory_base = [this]() { return this->memory_base; };
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this->pci_rd_memory_limit = [this]() { return this->memory_limit; };
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this->pci_rd_io_base = [this]() { return this->io_base; };
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this->pci_rd_io_limit = [this]() { return this->io_limit; };
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this->pci_rd_pref_mem_base = [this]() { return this->pref_mem_base; };
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this->pci_rd_pref_mem_limit = [this]() { return this->pref_mem_limit; };
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this->pci_rd_io_base_upper16 = [this]() { return this->io_base_upper16; };
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this->pci_rd_io_limit_upper16 = [this]() { return this->io_limit_upper16; };
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this->pci_rd_pref_base_upper32 = [this]() { return this->pref_base_upper32; };
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this->pci_rd_pref_limit_upper32 = [this]() { return this->pref_limit_upper32; };
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this->pci_rd_bridge_control = [this]() { return this->bridge_control; };
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this->pci_wr_primary_bus = [this](uint8_t val) { this->primary_bus = val; };
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this->pci_wr_secondary_bus = [this](uint8_t val) { this->secondary_bus = val; };
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this->pci_wr_subordinate_bus = [this](uint8_t val) { this->subordinate_bus = val; };
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this->pci_wr_sec_latency_timer = [this](uint8_t val) {
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this->sec_latency_timer = (this->sec_latency_timer & ~this->sec_latency_timer_cfg) |
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(val & this->sec_latency_timer_cfg);
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};
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this->pci_wr_sec_status = [this](uint16_t val) {};
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this->pci_wr_memory_base = [this](uint16_t val) {
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this->memory_base = (val & this->memory_cfg) | (this->memory_cfg & 15);
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this->memory_base_32 = ((this->memory_base & 0xfff0) << 16);
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};
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this->pci_wr_memory_limit = [this](uint16_t val) {
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this->memory_limit = (val & this->memory_cfg) | (this->memory_cfg & 15);
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this->memory_limit_32 = ((this->memory_limit & 0xfff0) << 16) + 0x100000;
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};
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this->pci_wr_io_base = [this](uint8_t val) {
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this->io_base = (val & this->io_cfg) | (this->io_cfg & 15);
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this->io_base_32 = ((uint32_t)this->io_base_upper16 << 16) | ((this->io_base & 0xf0) << 8);
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};
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this->pci_wr_io_limit = [this](uint8_t val) {
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this->io_limit = (val & this->io_cfg) | (this->io_cfg & 15);
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this->io_limit_32 = (((uint32_t)this->io_limit_upper16 << 16) |
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((this->io_limit & 0xf0) << 8)) + 0x1000;
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};
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this->pci_wr_pref_mem_base = [this](uint16_t val) {
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this->pref_mem_base = (val & this->pref_mem_cfg) | (this->pref_mem_cfg & 15);
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this->pref_mem_base_64 = ((uint64_t)this->pref_base_upper32 << 32) |
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((this->pref_mem_base & 0xfff0) << 16);
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};
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this->pci_wr_pref_mem_limit = [this](uint16_t val) {
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this->pref_mem_limit = (val & this->pref_mem_cfg) | (this->pref_mem_cfg & 15);
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this->pref_mem_limit_64 = (((uint64_t)this->pref_limit_upper32 << 32) |
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((this->pref_mem_limit & 0xfff0) << 16)) + 0x100000;
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};
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this->pci_wr_io_base_upper16 = [this](uint16_t val) {
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if ((this->io_base & 15) == 1)
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this->io_base_upper16 = val;
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this->io_base_32 = ((uint32_t)this->io_base_upper16 << 16) |
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((this->io_base & 0xf0) << 8);
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};
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this->pci_wr_io_limit_upper16 = [this](uint16_t val) {
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if ((this->io_limit & 15) == 1)
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this->io_limit_upper16 = val;
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this->io_limit_32 = (((uint32_t)this->io_limit_upper16 << 16) |
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((this->io_limit & 0xf0) << 8)) + 0x1000;
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};
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this->pci_wr_pref_base_upper32 = [this](uint32_t val) {
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if ((this->pref_mem_cfg & 15) == 1)
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this->pref_base_upper32 = val;
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this->pref_mem_base_64 = ((uint64_t)this->pref_base_upper32 << 32) |
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((this->pref_mem_base & 0xfff0) << 16);
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};
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this->pci_wr_pref_limit_upper32 = [this](uint32_t val) {
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if ((this->pref_mem_cfg & 15) == 1)
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this->pref_limit_upper32 = val;
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this->pref_mem_limit_64 = (((uint64_t)this->pref_limit_upper32 << 32) |
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((this->pref_mem_limit & 0xfff0) << 16)) + 0x100000;
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};
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this->pci_wr_bridge_control = [this](uint16_t val) { this->bridge_control = val; };
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};
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bool PCIBridge::pci_register_mmio_region(uint32_t start_addr, uint32_t size, PCIDevice* obj)
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{
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// FIXME: constrain region to memory range
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return this->host_instance->pci_register_mmio_region(start_addr, size, obj);
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}
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bool PCIBridge::pci_unregister_mmio_region(uint32_t start_addr, uint32_t size, PCIDevice* obj)
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{
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return this->host_instance->pci_unregister_mmio_region(start_addr, size, obj);
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}
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uint32_t PCIBridge::pci_cfg_read(uint32_t reg_offs, AccessDetails &details)
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{
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if (reg_offs < 0x18) {
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return PCIDevice::pci_cfg_read(reg_offs, details);
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}
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switch (reg_offs) {
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case PCI_CFG_PRIMARY_BUS:
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return (this->pci_rd_sec_latency_timer() << 24) |
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(this->pci_rd_subordinate_bus() << 16) |
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(this->pci_rd_secondary_bus() << 8) |
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(this->pci_rd_primary_bus());
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case PCI_CFG_IO_BASE:
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return (this->pci_rd_sec_status() << 16) |
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(this->pci_rd_io_limit() << 8) | (this->pci_rd_io_base());
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case PCI_CFG_MEMORY_BASE:
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return (this->pci_rd_memory_limit() << 16) | (this->pci_rd_memory_base());
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case PCI_CFG_PREF_MEM_BASE:
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return (this->pci_rd_pref_mem_limit() << 16) | (this->pci_rd_pref_mem_base());
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case PCI_CFG_PREF_BASE_UPPER32:
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return this->pci_rd_pref_base_upper32();
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case PCI_CFG_PREF_LIMIT_UPPER32:
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return this->pci_rd_pref_limit_upper32();
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case PCI_CFG_IO_BASE_UPPER16:
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return (this->pci_rd_io_limit_upper16() << 16) | (this->pci_rd_io_base_upper16());
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case PCI_CFG_CAP_PTR:
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return cap_ptr;
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case PCI_CFG_BRIDGE_ROM_ADDRESS:
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return exp_rom_bar;
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case PCI_CFG_INTERRUPT_LINE:
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return (this->pci_rd_bridge_control() << 16) | (irq_pin << 8) | irq_line;
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}
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LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER();
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return 0;
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}
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void PCIBridge::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details)
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{
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if (reg_offs < 0x18) {
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return PCIDevice::pci_cfg_write(reg_offs, value, details);
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}
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switch (reg_offs) {
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case PCI_CFG_PRIMARY_BUS:
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this->pci_wr_sec_latency_timer(value >> 24);
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this->pci_wr_subordinate_bus(value >> 16);
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this->pci_wr_secondary_bus(value >> 8);
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this->pci_wr_primary_bus(value & 0xFFU);
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break;
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case PCI_CFG_IO_BASE:
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this->pci_wr_sec_status(value >> 16);
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this->pci_wr_io_limit(value >> 8);
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this->pci_wr_io_base(value & 0xFFU);
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break;
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case PCI_CFG_MEMORY_BASE:
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this->pci_wr_memory_limit(value >> 16);
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this->pci_wr_memory_base(value & 0xFFFFU);
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break;
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case PCI_CFG_PREF_MEM_BASE:
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this->pci_wr_pref_mem_limit(value >> 16);
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this->pci_wr_pref_mem_base(value & 0xFFFFU);
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break;
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case PCI_CFG_PREF_BASE_UPPER32:
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this->pci_wr_pref_base_upper32(value);
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break;
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case PCI_CFG_PREF_LIMIT_UPPER32:
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this->pci_wr_pref_limit_upper32(value);
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break;
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case PCI_CFG_IO_BASE_UPPER16:
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this->pci_wr_io_limit_upper16(value >> 16);
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this->pci_wr_io_base_upper16(value & 0xFFFFU);
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break;
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case PCI_CFG_BRIDGE_ROM_ADDRESS:
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this->pci_wr_exp_rom_bar(value);
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break;
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case PCI_CFG_INTERRUPT_LINE:
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this->irq_line = value >> 24;
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this->pci_wr_bridge_control(value >> 16);
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break;
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default:
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LOG_WRITE_UNIMPLEMENTED_CONFIG_REGISTER();
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}
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}
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bool PCIBridge::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res)
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{
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if (!(this->command & 1)) return false;
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if (offset < this->io_base_32 || offset + size >= this->io_limit_32) return false;
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return this->pci_io_read_loop(offset, size, *res);
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}
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bool PCIBridge::pci_io_write(uint32_t offset, uint32_t value, uint32_t size)
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{
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if (!(this->command & 1)) return false;
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if (offset < this->io_base_32 || offset + size >= this->io_limit_32) return false;
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return this->pci_io_read_loop(offset, size, value);
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}
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