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90 lines
2.6 KiB
C++
90 lines
2.6 KiB
C++
//DingusPPC - Prototype 5bf2
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//Written by divingkatae
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//(c)2018-20 (theweirdo)
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//Please ask for permission
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//if you want to distribute this.
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//(divingkatae#1017 on Discord)
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/** MPC106 (Grackle) emulation
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Author: Max Poliakovski
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Grackle IC is a combined memory and PCI controller manufactured by Motorola.
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It's the central device in the Gossamer architecture.
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Manual: https://www.nxp.com/docs/en/reference-manual/MPC106UM.pdf
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This code emulate as much functionality as needed to run PowerMac Beige G3.
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This implies that
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- we only support address map B
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- our virtual device reports revision 4.0 as expected by machine firmware
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*/
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#ifndef MPC106_H_
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#define MPC106_H_
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#include <cinttypes>
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#include <unordered_map>
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#include "memctrlbase.h"
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#include "mmiodevice.h"
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#include "pcidevice.h"
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#include "pcihost.h"
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class MPC106 : public MemCtrlBase, public PCIDevice, public PCIHost
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{
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public:
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using MemCtrlBase::name;
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MPC106();
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~MPC106();
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uint32_t read(uint32_t offset, int size);
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void write(uint32_t offset, uint32_t value, int size);
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/* PCI host bridge API */
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bool pci_register_device(int dev_num, PCIDevice *dev_instance);
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protected:
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/* PCI access */
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uint32_t pci_read(uint32_t size);
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void pci_write(uint32_t value, uint32_t size);
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/* my own PCI configuration registers access */
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uint32_t pci_cfg_read(uint32_t reg_offs, uint32_t size);
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size);
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void set_host(PCIHost *host_instance) {}; // unimplemented for now
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/* PCI host bridge API */
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//bool pci_register_device(int dev_num, PCIDevice *dev_instance);
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bool pci_register_mmio_region(uint32_t start_addr, uint32_t size, PCIDevice *obj);
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private:
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uint8_t my_pci_cfg_hdr[256] = {
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0x57, 0x10, // vendor ID: Motorola
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0x02, 0x00, // device ID: MPC106
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0x06, 0x00, // PCI command
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0x80, 0x00, // PCI status
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0x40, // revision ID: 4.0
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0x00, // standard programming
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0x00, // subclass code: host bridge
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0x06, // class code: bridge device
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[0x73] = 0xCD, // default value for ODCR
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[0xA8] = 0x10, 0x00, 0x00, 0xFF, // PICR1
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[0xAC] = 0x0C, 0x06, 0x0C, 0x00, // PICR2
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[0xBA] = 0x04,
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[0xC0] = 0x01,
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[0xE0] = 0x42, 0x00, 0xFF, 0x0F,
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[0xE8] = 0x20,
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[0xF0] = 0x00, 0x00, 0x02, 0xFF,
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[0xF4] = 0x03,
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[0xFC] = 0x00, 0x00, 0x10, 0x00
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};
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uint32_t config_addr;
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//uint32_t config_data;
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std::unordered_map<int, PCIDevice*> pci_0_bus;
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};
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#endif
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