mirror of
https://github.com/dingusdev/dingusppc.git
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530 lines
19 KiB
C++
530 lines
19 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file TNT on-board video output emulation. */
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/** TNT on-board video comprises several components:
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- Chaos ASIC that provides data bus buffering between the video subsystem
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and the processor bus
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- Control ASIC that provides addressing and control for the video subsystem
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- RaDACal RAMDAC ASIC for generating RGB video stream to the monitor
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- Athens clock generator for generating pixel clock
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Some TNT boards can generate composite video output and thus include
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two additional components:
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- Sixty6 ASIC that converts RGB pixels stored in the VRAM to YUV color space
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- SAA7187 encoder that converts pixels from Sixty6 to composite video signal
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Kudos to joevt#3510 for his precious technical help and HW hacking.
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*/
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#include <devices/common/i2c/athens.h>
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#include <devices/common/i2c/i2c.h>
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#include <devices/deviceregistry.h>
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#include <devices/ioctrl/macio.h>
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#include <devices/video/control.h>
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#include <endianswap.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <machines/machineproperties.h>
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#include <memaccess.h>
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#include <cinttypes>
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namespace loguru {
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enum : Verbosity {
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Verbosity_RADACAL = loguru::Verbosity_INFO,
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Verbosity_CONTROL = loguru::Verbosity_INFO
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};
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}
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ControlVideo::ControlVideo()
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: PCIDevice("Control-Video"), VideoCtrlBase(640, 480)
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{
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supports_types(HWCompType::PCI_HOST | HWCompType::PCI_DEV);
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// get VRAM size in MBs and convert it to bytes
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this->vram_size = GET_INT_PROP("gfxmem_size") << 20;
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// calculate number of VRAM banks from VRAM size
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this->num_banks = this->vram_size >> 21; // 2 MB => 1 bank, 4 MB >> 2 banks
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// allocate VRAM
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this->vram_ptr = std::unique_ptr<uint8_t[]> (new uint8_t[this->vram_size]);
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// set up PCI configuration space header
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this->vendor_id = PCI_VENDOR_APPLE;
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this->device_id = 3;
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this->class_rev = 0;
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this->setup_bars({
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{0, 0xFFFFFFFFUL}, // I/O region (4 bytes but it's weird because bit 1 is set)
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{1, 0xFFFFF000UL}, // base address for the HW registers (4KB)
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{2, 0xFC000000UL} // base address for the VRAM (64MB)
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});
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this->pci_notify_bar_change = [this](int bar_num) {
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this->notify_bar_change(bar_num);
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};
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// initialize the video clock generator
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this->clk_gen = std::unique_ptr<AthensClocks> (new AthensClocks(0x28));
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// register the video clock generator with the I2C host
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I2CBus* i2c_bus = dynamic_cast<I2CBus*>(gMachineObj->get_comp_by_type(HWCompType::I2C_HOST));
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i2c_bus->register_device(0x28, this->clk_gen.get());
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// attach RAMDAC
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this->radacal = std::unique_ptr<AppleRamdac>(new AppleRamdac(DacFlavour::RADACAL));
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this->radacal->get_clut_entry_cb = [this](uint8_t index, uint8_t *colors) {
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uint8_t a;
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this->get_palette_color(index, colors[0], colors[1], colors[2], a);
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};
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this->radacal->set_clut_entry_cb = [this](uint8_t index, uint8_t *colors) {
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this->set_palette_color(index, colors[0], colors[1], colors[2], 0xFF);
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};
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this->radacal->cursor_ctrl_cb = [this](bool cursor_on) {
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if (cursor_on) {
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this->radacal->measure_hw_cursor(this->fb_ptr - 16);
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this->cursor_ovl_cb = [this](uint8_t *dst_buf, int dst_pitch) {
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this->radacal->draw_hw_cursor(this->fb_ptr - 16,
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dst_buf, dst_pitch);
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};
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} else {
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this->cursor_ovl_cb = nullptr;
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}
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};
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// attach IOBus Device #2 0xF301B000 ; register RaDACal with the I/O controller
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GrandCentral* gc_obj = dynamic_cast<GrandCentral*>(gMachineObj->get_comp_by_name("GrandCentral"));
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gc_obj->attach_iodevice(1, this->radacal.get());
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// initialize display identification
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this->display_id = std::unique_ptr<DisplayID> (new DisplayID());
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}
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void ControlVideo::notify_bar_change(int bar_num) {
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switch (bar_num) {
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case 0:
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this->io_base = this->bars[bar_num] & ~3;
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LOG_F(INFO, "Control: I/O space address set to 0x%08X", this->io_base);
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break;
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case 1:
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if (this->regs_base != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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this->regs_base = this->bars[bar_num] & 0xFFFFFFF0UL;
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this->host_instance->pci_register_mmio_region(this->regs_base,
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0x1000, this);
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LOG_F(INFO, "Control: register aperture set to 0x%08X", this->regs_base);
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}
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break;
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case 2:
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if (this->vram_base != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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this->vram_base = this->bars[bar_num] & 0xFFFFFFF0UL;
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this->host_instance->pci_register_mmio_region(this->vram_base,
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0x04000000, this);
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LOG_F(INFO, "Control: VRAM aperture set to 0x%08X", this->vram_base);
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}
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break;
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}
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}
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int ControlVideo::device_postinit() {
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this->int_ctrl = dynamic_cast<InterruptCtrl*>(
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gMachineObj->get_comp_by_type(HWCompType::INT_CTRL));
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this->irq_id = this->int_ctrl->register_dev_int(IntSrc::CONTROL);
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this->vbl_cb = [this](uint8_t irq_line_state) {
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if (irq_line_state != !!(this->int_status & VBL_IRQ_STAT)) {
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if (irq_line_state)
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this->int_status |= VBL_IRQ_STAT;
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else
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this->int_status &= ~VBL_IRQ_STAT;
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if (this->int_enable & VBL_IRQ_EN)
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this->int_ctrl->ack_int(this->irq_id, irq_line_state);
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}
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};
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return 0;
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}
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static const char * get_name_controlreg(int offset) {
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switch (offset >> 4) {
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case ControlRegs::CUR_LINE : return "CUR_LINE";
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case ControlRegs::VFPEQ : return "VFPEQ";
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case ControlRegs::VFP : return "VFP";
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case ControlRegs::VAL : return "VAL";
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case ControlRegs::VBP : return "VBP";
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case ControlRegs::VBPEQ : return "VBPEQ";
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case ControlRegs::VSYNC : return "VSYNC";
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case ControlRegs::VHLINE : return "VHLINE";
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case ControlRegs::PIPE_DELAY : return "PIPE_DELAY";
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case ControlRegs::HPIX : return "HPIX";
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case ControlRegs::HFP : return "HFP";
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case ControlRegs::HAL : return "HAL";
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case ControlRegs::HBWAY : return "HBWAY";
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case ControlRegs::HSP : return "HSP";
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case ControlRegs::HEQ : return "HEQ";
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case ControlRegs::HLFLN : return "HLFLN";
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case ControlRegs::HSERR : return "HSERR";
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case ControlRegs::CNTTST : return "CNTTST";
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case ControlRegs::SWATCH_CTRL : return "SWATCH_CTRL";
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case ControlRegs::GBASE : return "GBASE";
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case ControlRegs::ROW_WORDS : return "ROW_WORDS";
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case ControlRegs::MON_SENSE : return "MON_SENSE";
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case ControlRegs::MISC_ENABLES : return "MISC_ENABLES";
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case ControlRegs::GSC_DIVIDE : return "GSC_DIVIDE";
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case ControlRegs::REFRESH_COUNT : return "REFRESH_COUNT";
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case ControlRegs::INT_ENABLE : return "INT_ENABLE";
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case ControlRegs::INT_STATUS : return "INT_STATUS";
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default : return "unknown";
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}
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}
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uint32_t ControlVideo::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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if (rgn_start == this->vram_base) {
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if (offset >= 0x800000) {
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// HACK: writing to VRAM in 128bit mode with only the standard
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// bank populated seems to replicate the first 64bit portion of data
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// in the second 64bit portion. This "feature" is used by
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// the Mac OS driver to detect how much physical VRAM is installed.
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// I handle this case here because reads from VRAM seem to happen
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// far less frequently than writes.
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if ((this->enables & VRAM_WIDE_MODE) && this->num_banks == 1)
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offset &= ~8UL;
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return read_mem(&this->vram_ptr[offset & 0x3FFFFF], size);
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}
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LOG_F(ERROR, "%s: read from unmapped aperture address 0x%X", this->name.c_str(),
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this->vram_base + offset);
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return 0;
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}
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uint32_t value;
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if (rgn_start == this->regs_base) {
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switch (offset >> 4) {
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case ControlRegs::CUR_LINE:
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value = 0; // current active video line should relate this to refresh rate
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LOG_F(ERROR, "Control: read CUR_LINE %03x", offset);
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break;
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case ControlRegs::VFPEQ:
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case ControlRegs::VFP:
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case ControlRegs::VAL:
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case ControlRegs::VBP:
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case ControlRegs::VBPEQ:
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case ControlRegs::VSYNC:
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case ControlRegs::VHLINE:
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case ControlRegs::PIPE_DELAY:
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case ControlRegs::HPIX:
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case ControlRegs::HFP:
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case ControlRegs::HAL:
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case ControlRegs::HBWAY:
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case ControlRegs::HSP:
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case ControlRegs::HEQ:
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case ControlRegs::HLFLN:
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case ControlRegs::HSERR:
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value = this->swatch_params[(offset >> 4) - ControlRegs::VFPEQ];
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break;
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case ControlRegs::CNTTST:
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value = 0;
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break;
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case ControlRegs::SWATCH_CTRL:
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value = this->swatch_ctrl;
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break;
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case ControlRegs::GBASE:
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value = this->fb_base;
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break;
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case ControlRegs::ROW_WORDS:
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value = this->row_words;
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break;
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case ControlRegs::MON_SENSE:
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value = this->cur_mon_id << 6;
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break;
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case ControlRegs::MISC_ENABLES:
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value = this->enables;
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break;
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case ControlRegs::GSC_DIVIDE:
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value = this->clock_divider;
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break;
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case ControlRegs::REFRESH_COUNT:
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value = 0;
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break;
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case ControlRegs::INT_STATUS:
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value = this->int_status;
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break;
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case ControlRegs::INT_ENABLE:
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value = this->int_enable;
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break;
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default:
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LOG_F(ERROR, "Control: read %03x", offset);
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value = 0;
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}
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AccessDetails details;
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details.size = size;
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details.offset = offset & 3;
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uint32_t result = pci_conv_rd_data(value, value, details);
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if ((offset & 3) || (size != 4)) {
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LOG_F(WARNING, "%s: read %s %03x.%c = %08x -> %0*x", this->name.c_str(), get_name_controlreg(offset), offset, SIZE_ARG(size), value, size * 2, result);
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}
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return result;
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}
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return 0;
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}
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void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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if (rgn_start == this->vram_base) {
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if (offset >= 0x800000) {
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write_mem(&this->vram_ptr[offset & 0x3FFFFF], value, size);
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} else {
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LOG_F(ERROR, "%s: write to unmapped aperture address 0x%X", this->name.c_str(),
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this->vram_base + offset);
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}
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return;
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}
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if (rgn_start == this->regs_base) {
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value = BYTESWAP_32(value);
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switch (offset >> 4) {
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case ControlRegs::PIPE_DELAY:
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this->swatch_params[(offset >> 4) - ControlRegs::VFPEQ] = value & 0x3FF;
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break;
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case ControlRegs::HEQ:
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this->swatch_params[(offset >> 4) - ControlRegs::VFPEQ] = value & 0xFFU;
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break;
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case ControlRegs::VFPEQ:
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case ControlRegs::VFP:
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case ControlRegs::VAL:
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case ControlRegs::VBP:
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case ControlRegs::VBPEQ:
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case ControlRegs::VSYNC:
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case ControlRegs::VHLINE:
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case ControlRegs::HPIX:
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case ControlRegs::HFP:
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case ControlRegs::HAL:
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case ControlRegs::HBWAY:
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case ControlRegs::HSP:
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case ControlRegs::HLFLN:
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case ControlRegs::HSERR:
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this->swatch_params[(offset >> 4) - ControlRegs::VFPEQ] = value & 0xFFF;
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break;
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case ControlRegs::CNTTST:
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if (value)
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LOG_F(WARNING, "%s: CNTTST set to 0x%X", this->name.c_str(), value);
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break;
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case ControlRegs::SWATCH_CTRL:
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if ((this->swatch_ctrl ^ value) & DISABLE_TIMING) {
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this->swatch_ctrl = value;
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this->strobe_counter = 0;
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} else if ((this->swatch_ctrl ^ value) & RESET_TIMING) {
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this->swatch_ctrl = value;
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if (value & RESET_TIMING) { // count 0-to-1 transitions
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this->strobe_counter++;
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if (this->strobe_counter >= 2) {
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if (value & DISABLE_TIMING)
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disable_display();
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else
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enable_display();
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}
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}
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} else
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this->swatch_ctrl = value;
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break;
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case ControlRegs::GBASE:
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this->fb_base = value & 0x3FFFE0;
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break;
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case ControlRegs::ROW_WORDS:
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this->row_words = value & 0x7FE0;
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break;
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case ControlRegs::MON_SENSE: {
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uint8_t dirs = ((value >> 3) & 7) ^ 7;
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uint8_t levels = ((value & 7) & dirs) | (dirs ^ 7);
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this->cur_mon_id = this->display_id->read_monitor_sense(levels, dirs);
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}
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break;
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case ControlRegs::MISC_ENABLES:
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if ((this->enables ^ value) & BLANK_DISABLE) {
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if (value & BLANK_DISABLE)
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this->blank_on = false;
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else {
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this->blank_on = true;
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this->blank_display();
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}
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}
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this->enables = value;
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if (this->enables & FB_ENDIAN_LITTLE)
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ABORT_F("%s: little-endian framebuffer is not implemented yet",
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this->name.c_str());
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break;
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case ControlRegs::GSC_DIVIDE:
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this->clock_divider = value & 3;
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break;
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case ControlRegs::REFRESH_COUNT:
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LOG_F(9, "Control: VRAM refresh count set to %d", value);
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break;
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case ControlRegs::INT_ENABLE:
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if ((this->int_enable ^ value) & VBL_IRQ_CLR) {
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// clear VBL IRQ on a 1-to-0 transition of INT_ENABLE[VBL_IRQ_CLR]
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if (!(value & VBL_IRQ_CLR))
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this->vbl_cb(0);
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}
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this->int_enable = value & 0x0F;
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break;
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default:
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LOG_F(ERROR, "Control: write %03x = %0*x", offset, size * 2, value);
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}
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}
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}
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uint8_t* ControlVideo::GetVram()
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{
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return &this->vram_ptr[0];
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}
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void ControlVideo::enable_display()
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{
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int new_width, new_height, clk_divisor;
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// get pixel frequency from Athens
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this->pixel_clock = this->clk_gen->get_dot_freq();
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// get RaDACal clock divisor
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clk_divisor = this->radacal->get_clock_div();
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// calculate active_width and active_height from video timing parameters
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new_width = swatch_params[ControlRegs::HFP-1] - swatch_params[ControlRegs::HAL-1];
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new_height = swatch_params[ControlRegs::VFP-1] - swatch_params[ControlRegs::VAL-1];
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new_width *= clk_divisor;
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if (this->enables & SCAN_CONTROL) {
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new_height >>= 1;
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}
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this->active_width = new_width;
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this->active_height = new_height;
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// set framebuffer parameters
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this->fb_ptr = &this->vram_ptr[this->fb_base];
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this->fb_pitch = this->row_words;
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this->pixel_depth = this->radacal->get_pix_width();
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if (swatch_params[ControlRegs::HAL-1] != swatch_params[ControlRegs::PIPE_DELAY-1] + 1 || this->pixel_depth == 32) {
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// don't know how to calculate offset from GBASE (fb_base); it is always hard coded as + 16 in the ndrv.
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this->fb_ptr += 16; // first 16 bytes are for 4 bpp HW cursor
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}
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else {
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/*
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Open Firmware frame buffer has these properties:
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- GBASE == 0 // no offset from vram_ptr
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- fb_ptr == vram_ptr // no offset from GBASE
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- active_width == ROW_WORDS (row_words) // no offset between rows
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- HAL == PIPE_DELAY + 1
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- depth_mode = 0 // 8 bit indexed
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*/
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}
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// get pixel depth from RaDACal
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switch (this->pixel_depth) {
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case 8:
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this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
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this->convert_frame_8bpp_indexed(dst_buf, dst_pitch);
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};
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break;
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case 16:
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this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
|
|
this->convert_frame_15bpp_BE(dst_buf, dst_pitch);
|
|
};
|
|
break;
|
|
case 32:
|
|
this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
|
|
this->convert_frame_32bpp_BE(dst_buf, dst_pitch);
|
|
};
|
|
break;
|
|
default:
|
|
LOG_F(ERROR, "RaDACal: Invalid pixel depth code!");
|
|
}
|
|
|
|
// calculate display refresh rate
|
|
this->hori_blank = swatch_params[ControlRegs::HAL-1] +
|
|
(swatch_params[ControlRegs::HSP-1] - swatch_params[ControlRegs::HFP-1]);
|
|
|
|
this->hori_blank *= clk_divisor;
|
|
|
|
this->vert_blank = swatch_params[ControlRegs::VAL-1] +
|
|
(swatch_params[ControlRegs::VSYNC-1] - swatch_params[ControlRegs::VFP-1]);
|
|
|
|
if (this->enables & SCAN_CONTROL) {
|
|
this->vert_blank >>= 1;
|
|
}
|
|
|
|
this->hori_total = this->hori_blank + new_width;
|
|
this->vert_total = this->vert_blank + new_height;
|
|
|
|
this->radacal->set_fb_parameters(active_width, active_height, this->fb_pitch);
|
|
|
|
this->stop_refresh_task();
|
|
|
|
// set up periodic timer for display updates
|
|
if (this->active_width > 0 && this->active_height > 0 && this->pixel_clock > 0) {
|
|
this->refresh_rate = (double)(this->pixel_clock) / (this->hori_total * this->vert_total);
|
|
LOG_F(INFO, "Control: refresh rate set to %f Hz", this->refresh_rate);
|
|
|
|
this->start_refresh_task();
|
|
|
|
this->blank_on = false;
|
|
|
|
LOG_F(CONTROL, "Control: display enabled");
|
|
this->crtc_on = true;
|
|
}
|
|
else {
|
|
LOG_F(CONTROL, "Control: display not enabled");
|
|
this->blank_on = true;
|
|
this->crtc_on = false;
|
|
}
|
|
}
|
|
|
|
void ControlVideo::disable_display()
|
|
{
|
|
this->crtc_on = false;
|
|
LOG_F(INFO, "Control: display disabled");
|
|
}
|
|
|
|
// ========================== Device registry stuff ==========================
|
|
|
|
static const PropMap Control_Properties = {
|
|
{"gfxmem_size",
|
|
new IntProperty( 2, vector<uint32_t>({2, 4}))},
|
|
{"mon_id",
|
|
new StrProperty("AppleVision1710")},
|
|
};
|
|
|
|
static const DeviceDescription Control_Descriptor = {
|
|
ControlVideo::create, {}, Control_Properties
|
|
};
|
|
|
|
REGISTER_DEVICE(ControlVideo, Control_Descriptor);
|