mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-09-04 06:29:50 +00:00
766 lines
25 KiB
C++
766 lines
25 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** Apple memory-mapped I/O controller emulation.
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Author: Max Poliakovski
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*/
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#include <core/timermanager.h>
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#include <cpu/ppc/ppcemu.h>
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#include <cpu/ppc/ppcmmu.h>
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#include <devices/deviceregistry.h>
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#include <devices/common/hwcomponent.h>
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#include <devices/common/scsi/sc53c94.h>
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#include <devices/common/viacuda.h>
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#include <devices/ethernet/mace.h>
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#include <devices/floppy/swim3.h>
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#include <devices/ioctrl/amic.h>
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#include <devices/serial/escc.h>
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#include <machines/machinebase.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <devices/video/displayid.h>
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#include <devices/video/pdmonboard.h>
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#include <algorithm>
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#include <cinttypes>
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#include <loguru.hpp>
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#include <memory>
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AMIC::AMIC() : MMIODevice()
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{
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this->set_name("Apple Memory-mapped I/O Controller");
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supports_types(HWCompType::MMIO_DEV | HWCompType::INT_CTRL);
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// connect internal SCSI controller
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this->scsi = dynamic_cast<Sc53C94*>(gMachineObj->get_comp_by_name("Sc53C94"));
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this->curio_dma = std::unique_ptr<AmicScsiDma> (new AmicScsiDma());
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this->scsi->set_dma_channel(this->curio_dma.get());
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this->scsi->set_drq_callback([this](const uint8_t drq_state) {
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if (drq_state & 1)
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via2_ifr |= VIA2_INT_SCSI_DRQ;
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else
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via2_ifr &= ~VIA2_INT_SCSI_DRQ;
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this->update_via2_irq();
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});
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// connect serial HW
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this->escc = dynamic_cast<EsccController*>(gMachineObj->get_comp_by_name("Escc"));
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this->escc_xmit_b_dma = std::unique_ptr<AmicSerialXmitDma>(new AmicSerialXmitDma("EsccBXmit"));
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this->escc_xmit_a_dma = std::unique_ptr<AmicSerialXmitDma>(new AmicSerialXmitDma("EsccAXmit"));
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// connect Ethernet HW
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this->mace = dynamic_cast<MaceController*>(gMachineObj->get_comp_by_name("Mace"));
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// connect Cuda
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this->viacuda = dynamic_cast<ViaCuda*>(gMachineObj->get_comp_by_name("ViaCuda"));
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// initialize sound HW
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this->snd_out_dma = std::unique_ptr<AmicSndOutDma> (new AmicSndOutDma());
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this->snd_out_dma->init_interrupts(this, 2 << 8);
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this->awacs = std::unique_ptr<AwacDevicePdm> (new AwacDevicePdm());
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this->awacs->set_dma_out(this->snd_out_dma.get());
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// initialize on-board video
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this->disp_id = std::unique_ptr<DisplayID> (new DisplayID());
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this->def_vid = std::unique_ptr<PdmOnboardVideo> (new PdmOnboardVideo());
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this->def_vid->init_interrupts(this, SLOT_INT_VBL << 16);
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// initialize floppy disk HW
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this->swim3 = dynamic_cast<Swim3::Swim3Ctrl*>(gMachineObj->get_comp_by_name("Swim3"));
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this->floppy_dma = std::unique_ptr<AmicFloppyDma> (new AmicFloppyDma());
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this->swim3->set_dma_channel(this->floppy_dma.get());
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}
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AMIC::~AMIC()
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{
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if (this->pseudo_vbl_tid) {
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TimerManager::get_instance()->cancel_timer(this->pseudo_vbl_tid);
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this->pseudo_vbl_tid = 0;
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}
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}
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int AMIC::device_postinit()
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{
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MemCtrlBase *mem_ctrl = dynamic_cast<MemCtrlBase *>
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(gMachineObj->get_comp_by_type(HWCompType::MEM_CTRL));
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// add memory mapped I/O region for the AMIC control registers
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if (!mem_ctrl->add_mmio_region(0x50F00000, 0x00040000, this)) {
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LOG_F(ERROR, "Couldn't register AMIC registers!");
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}
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// AMIC drives the VIA CA1 internally to generate 60.15 Hz interrupts
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this->pseudo_vbl_tid = TimerManager::get_instance()->add_cyclic_timer(
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static_cast<uint64_t>((1.0f/60.15) * NS_PER_SEC + 0.5f),
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[this]() {
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this->viacuda->assert_ctrl_line(ViaLine::CA1);
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});
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// set EMMO pin status (active low)
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this->emmo_pin = GET_BIN_PROP("emmo") ^ 1;
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return 0;
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}
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uint32_t AMIC::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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uint32_t phase_val;
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// subdevices registers
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switch(offset >> 12) {
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case 0: // VIA1 registers
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case 1:
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return this->viacuda->read(offset >> 9);
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case 4: // SCC registers
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return this->escc->read(compat_to_macrisc[(offset >> 1) & 0xF]);
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case 0xA: // MACE registers
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return this->mace->read((offset >> 4) & 0x1F);
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case 0x10: // SCSI registers
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if (offset & 0x100) {
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return this->scsi->pseudo_dma_read();
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} else {
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return this->scsi->read((offset >> 4) & 0xF);
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}
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case 0x14: // Sound registers
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switch (offset) {
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case AMICReg::Snd_Stat_0:
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case AMICReg::Snd_Stat_1:
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case AMICReg::Snd_Stat_2:
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return (this->awacs->read_stat() >> (offset & 3) * 8) & 0xFF;
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case AMICReg::Snd_Phase0:
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case AMICReg::Snd_Phase1:
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case AMICReg::Snd_Phase2:
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// the sound phase register is organized as follows:
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// 000000oo oooooooo oopppppp where 'o' is the 12-bit offset
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// into the DMA buffer and 'p' is an undocumented prescale value
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// HWInit doesn't care about. Let's hope it will be sufficient
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// to return 0 for prescale.
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phase_val = this->snd_out_dma->get_cur_buf_pos() << 6;
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return (phase_val >> ((2 - (offset & 3)) * 8)) & 0xFF;
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case AMICReg::Snd_Out_Ctrl:
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return this->snd_out_ctrl;
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case AMICReg::Snd_Out_DMA:
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return this->snd_out_dma->read_stat();
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}
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break;
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case 0x16: // SWIM3 registers
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case 0x17:
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return this->swim3->read((offset >> 9) & 0xF);
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}
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switch(offset) {
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case AMICReg::Ariel_Config:
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return this->def_vid->get_vdac_config();
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case AMICReg::VIA2_Slot_IFR:
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return this->via2_slot_ifr;
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case AMICReg::VIA2_IFR:
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case AMICReg::VIA2_IFR_RBV:
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return this->via2_ifr;
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case AMICReg::VIA2_Slot_IER:
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return this->via2_slot_ier;
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case AMICReg::VIA2_IER:
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case AMICReg::VIA2_IER_RBV:
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return this->via2_ier;
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case AMICReg::Video_Mode:
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return this->def_vid->get_video_mode();
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case AMICReg::Monitor_Id:
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return this->mon_id;
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case AMICReg::Int_Ctrl:
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return (this->int_ctrl & 0xC0) | (this->dev_irq_lines & 0x3F);
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case AMICReg::DMA_IFR_0:
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return this->dma_ifr0;
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case AMICReg::DMA_IFR_1:
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return this->dma_ifr1;
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case AMICReg::Diag_Reg:
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return 0xFE | this->emmo_pin;
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case AMICReg::DMA_Base_Addr_0:
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case AMICReg::DMA_Base_Addr_1:
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case AMICReg::DMA_Base_Addr_2:
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case AMICReg::DMA_Base_Addr_3:
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return (this->dma_base >> (3 - (offset & 3)) * 8) & 0xFF;
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case AMICReg::SCSI_DMA_Ctrl:
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return this->curio_dma->read_stat();
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case AMICReg::Floppy_Addr_Ptr_0:
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case AMICReg::Floppy_Addr_Ptr_1:
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case AMICReg::Floppy_Addr_Ptr_2:
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case AMICReg::Floppy_Addr_Ptr_3:
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return (this->floppy_addr_ptr >> (3 - (offset & 3)) * 8) & 0xFF;
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case AMICReg::Floppy_DMA_Ctrl:
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return this->floppy_dma->read_stat();
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case SCC_DMA_Xmt_B_Ctrl:
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return this->escc_xmit_b_dma->read_stat();
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default:
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LOG_F(WARNING, "Unknown AMIC register read, offset=%x", offset);
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}
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return 0;
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}
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void AMIC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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uint32_t mask;
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// subdevices registers
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switch(offset >> 12) {
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case 0: // VIA1 registers
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case 1:
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this->viacuda->write(offset >> 9, value);
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return;
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case 4:
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this->escc->write(compat_to_macrisc[(offset >> 1) & 0xF], value);
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return;
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case 0xA: // MACE registers
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this->mace->write((offset >> 4) & 0x1F, value);
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return;
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case 0x10:
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if (offset & 0x100)
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this->scsi->pseudo_dma_write(value);
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else
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this->scsi->write((offset >> 4) & 0xF, value);
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return;
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case 0x14: // Sound registers
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switch(offset) {
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case AMICReg::Snd_Ctrl_0:
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case AMICReg::Snd_Ctrl_1:
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case AMICReg::Snd_Ctrl_2:
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// remember values of sound control registers
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this->imm_snd_regs[offset & 3] = value;
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// transfer control information to the sound codec when ready
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if ((this->imm_snd_regs[0] & 0xC0) == PDM_SND_CTRL_VALID) {
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this->awacs->write_ctrl(
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(this->imm_snd_regs[1] >> 4) | (this->imm_snd_regs[0] & 0x3F),
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((this->imm_snd_regs[1] & 0xF) << 8) | this->imm_snd_regs[2]
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);
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}
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return;
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case AMICReg::Snd_Buf_Size_Hi:
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case AMICReg::Snd_Buf_Size_Lo:
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SET_SIZE_BYTE(this->snd_buf_size, offset, value);
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this->snd_buf_size &= ~3; // sound buffer size is always a multiple of 4
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LOG_F(9, "AMIC: Sound buffer size set to 0x%X", this->snd_buf_size);
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return;
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case AMICReg::Snd_Out_Ctrl:
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if ((value & 1) != (this->snd_out_ctrl & 1)) {
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if (value & 1) {
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this->snd_out_dma->init(this->dma_base & ~0x3FFFF,
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this->snd_buf_size);
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this->snd_out_dma->enable();
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this->awacs->set_sample_rate((this->snd_out_ctrl >> 1) & 3);
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this->awacs->dma_out_start();
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} else {
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this->snd_out_dma->disable();
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this->awacs->dma_out_pause();
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}
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}
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this->snd_out_ctrl = value;
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return;
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case AMICReg::Snd_In_Ctrl:
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LOG_F(INFO, "AMIC Sound In Ctrl updated, val=%x", value);
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return;
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case AMICReg::Snd_Out_DMA:
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this->snd_out_dma->write_dma_out_ctrl(value);
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return;
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}
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case 0x16: // SWIM3 registers
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case 0x17:
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this->swim3->write((offset >> 9) & 0xF, value);
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return;
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}
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switch(offset) {
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case AMICReg::VIA2_Slot_IFR:
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if (value & SLOT_INT_VBL) {
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// clear pending VBL int
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this->ack_slot_int(SLOT_INT_VBL, 0);
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}
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break;
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case AMICReg::VIA2_IFR:
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// if bit 7 is set, clear the corresponding IRQ bit for each "1" in value
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if (value & 0x80) {
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this->via2_ifr &= ~(value & 0x7F);
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this->update_via2_irq();
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} else { // writing any value to VIA2_IFR with bit 7 cleared has no effect
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LOG_F(WARNING, "%s: bit 7 of VIA2_IFR is cleared!", this->name.c_str());
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}
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break;
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case AMICReg::VIA2_Slot_IER:
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if (value & 0x80)
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this->via2_slot_ier |= value & 0x7F;
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else
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this->via2_slot_ier &= ~value;
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break;
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case AMICReg::VIA2_IER:
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case AMICReg::VIA2_IER_RBV:
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if (value & 0x80) {
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this->via2_ier |= value & 0x7F;
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} else {
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this->via2_ier &= ~value;
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}
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this->update_via2_irq();
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break;
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case AMICReg::Ariel_Clut_Index:
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this->def_vid->set_clut_index(value);
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break;
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case AMICReg::Ariel_Clut_Color:
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this->def_vid->set_clut_color(value);
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break;
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case AMICReg::Ariel_Config:
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this->def_vid->set_vdac_config(value);
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break;
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case AMICReg::Video_Mode:
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this->def_vid->set_video_mode(value);
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break;
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case AMICReg::Pixel_Depth:
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this->def_vid->set_pixel_depth(value);
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break;
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case AMICReg::Monitor_Id: {
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// extract and convert pin directions (0 - input, 1 - output)
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uint8_t dirs = ~value & 7;
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if (!dirs && !(value & 8)) {
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LOG_F(INFO, "AMIC: Monitor sense lines tristated");
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}
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// propagate bit 3 to all pins configured as output
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// set levels of all intput pins to "1"
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uint8_t levels = (7 ^ dirs) | (((value & 8) ? 7 : 0) & dirs);
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// read monitor sense lines and store the result in the bits 4-6
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this->mon_id = (this->mon_id & 0xF) |
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(this->disp_id->read_monitor_sense(levels, dirs) << 4);
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}
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break;
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case AMICReg::Int_Ctrl:
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// reset CPU interrupt bit if requested
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if (value & CPU_INT_CLEAR) {
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if (this->int_ctrl & CPU_INT_FLAG) {
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this->int_ctrl &= ~CPU_INT_FLAG;
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ppc_release_int();
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LOG_F(5, "AMIC: CPU INT latch cleared");
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}
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}
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// keep interrupt mode bit
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// and discard read-only IQR state bits
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this->int_ctrl |= value & CPU_INT_MODE;
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break;
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case AMICReg::DMA_Base_Addr_0:
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case AMICReg::DMA_Base_Addr_1:
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case AMICReg::DMA_Base_Addr_2:
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case AMICReg::DMA_Base_Addr_3:
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SET_ADDR_BYTE(this->dma_base, offset, value);
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this->dma_base &= 0xFFFC0000UL;
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LOG_F(9, "AMIC: DMA base address set to 0x%X", this->dma_base);
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break;
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case AMICReg::Enet_DMA_Xmt_Ctrl:
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LOG_F(INFO, "AMIC Ethernet Transmit DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::SCSI_DMA_Base_0:
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case AMICReg::SCSI_DMA_Base_1:
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case AMICReg::SCSI_DMA_Base_2:
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case AMICReg::SCSI_DMA_Base_3:
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SET_ADDR_BYTE(this->scsi_dma_base, offset, value);
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this->scsi_dma_base &= 0xFFFFFFF8UL;
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LOG_F(9, "AMIC: SCSI DMA base address set to 0x%X", this->scsi_dma_base);
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break;
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case AMICReg::SCSI_DMA_Ctrl:
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if (value & 1) { // RST bit set?
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this->scsi_addr_ptr = this->scsi_dma_base;
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this->curio_dma->reset(this->scsi_addr_ptr);
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}
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if (value & 2) { // RUN bit set?
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this->curio_dma->reinit(this->scsi_dma_base);
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if (value & (1 << 6))
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this->scsi->real_dma_xfer_out();
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else
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this->scsi->real_dma_xfer_in();
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}
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this->curio_dma->write_ctrl(value);
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break;
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case AMICReg::Enet_DMA_Rcv_Ctrl:
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LOG_F(INFO, "AMIC Ethernet Receive DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::Floppy_Addr_Ptr_2:
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case AMICReg::Floppy_Addr_Ptr_3:
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SET_ADDR_BYTE(this->floppy_addr_ptr, offset, value);
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break;
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case AMICReg::Floppy_Byte_Cnt_Hi:
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case AMICReg::Floppy_Byte_Cnt_Lo:
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SET_SIZE_BYTE(this->floppy_byte_cnt, offset, value);
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break;
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case AMICReg::Floppy_DMA_Ctrl:
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if (value & 1) { // RST bit set?
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this->floppy_addr_ptr = this->dma_base + 0x15000;
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this->floppy_dma->reset(this->floppy_addr_ptr);
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}
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if (value & 2) { // RUN bit set?
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this->floppy_dma->reinit(this->floppy_addr_ptr, this->floppy_byte_cnt);
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}
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this->floppy_dma->write_ctrl(value);
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break;
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case AMICReg::SCC_DMA_Xmt_A_Ctrl:
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LOG_F(INFO, "AMIC SCC Transmit Ch A DMA Ctrl updated, val=%x", value);
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this->escc_xmit_a_dma->write_ctrl(value);
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break;
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case AMICReg::SCC_DMA_Rcv_A_Ctrl:
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LOG_F(INFO, "AMIC SCC Receive Ch A DMA Ctrl updated, val=%x", value);
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break;
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case AMICReg::SCC_DMA_Xmt_B_Ctrl:
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LOG_F(INFO, "AMIC SCC Transmit Ch B DMA Ctrl updated, val=%x", value);
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this->escc_xmit_b_dma->write_ctrl(value);
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break;
|
|
case AMICReg::SCC_DMA_Rcv_B_Ctrl:
|
|
LOG_F(INFO, "AMIC SCC Receive Ch B DMA Ctrl updated, val=%x", value);
|
|
break;
|
|
default:
|
|
LOG_F(WARNING, "Unknown AMIC register write, offset=%x, val=%x",
|
|
offset, value);
|
|
}
|
|
}
|
|
|
|
// ======================== Interrupt related stuff ==========================
|
|
uint32_t AMIC::register_dev_int(IntSrc src_id) {
|
|
switch (src_id) {
|
|
case IntSrc::VIA_CUDA:
|
|
return CPU_INT_VIA1;
|
|
case IntSrc::SCSI_CURIO:
|
|
return VIA2_INT_SCSI_IRQ << 8;
|
|
case IntSrc::SWIM3:
|
|
return VIA2_INT_SWIM3 << 8;
|
|
case IntSrc::NMI:
|
|
return CPU_INT_NMI;
|
|
default:
|
|
ABORT_F("AMIC: unknown interrupt source %d", src_id);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint32_t AMIC::register_dma_int(IntSrc src_id) {
|
|
ABORT_F("AMIC: register_dma_int() not implemented");
|
|
return 0;
|
|
}
|
|
|
|
void AMIC::ack_int(uint32_t irq_id, uint8_t irq_line_state) {
|
|
// dispatch cascaded AMIC interrupts from various sources
|
|
// irq_id format: 00DDCCBBAA where
|
|
// - AA -> CPU interrupts
|
|
// - BB -> pseudo VIA2 interrupts
|
|
// - CC -> slot interrupts
|
|
if (irq_id < 0x100) {
|
|
this->ack_cpu_int(irq_id, irq_line_state);
|
|
} else if (irq_id < 0x10000) {
|
|
this->ack_via2_int(irq_id >> 8, irq_line_state);
|
|
} else if (irq_id < 0x1000000) {
|
|
this->ack_slot_int(irq_id >> 16, irq_line_state);
|
|
} else {
|
|
ABORT_F("AMIC: unknown interrupt source ID 0x%X", irq_id);
|
|
}
|
|
}
|
|
|
|
void AMIC::ack_slot_int(uint32_t irq_id, uint8_t irq_line_state) {
|
|
// CAUTION: reverse logic (0 - true, 1 - false) in the IFR register!
|
|
if (irq_line_state) {
|
|
this->via2_slot_ifr &= ~irq_id;
|
|
} else {
|
|
this->via2_slot_ifr |= irq_id;
|
|
}
|
|
uint8_t new_irq = !!(~this->via2_slot_ifr & this->via2_slot_ier & 0x7F);
|
|
if (new_irq != this->via2_slot_irq) {
|
|
this->via2_slot_irq = new_irq;
|
|
this->ack_via2_int(VIA2_INT_ALL_SLOT, new_irq);
|
|
}
|
|
}
|
|
|
|
void AMIC::update_via2_irq() {
|
|
uint8_t new_irq = !!(this->via2_ifr & this->via2_ier & 0x7F);
|
|
this->via2_ifr = (this->via2_ifr & 0x7F) | (new_irq << 7);
|
|
if (new_irq != this->via2_irq) {
|
|
this->via2_irq = new_irq;
|
|
this->ack_cpu_int(CPU_INT_VIA2, new_irq);
|
|
}
|
|
}
|
|
|
|
void AMIC::ack_via2_int(uint32_t irq_id, uint8_t irq_line_state) {
|
|
if (irq_line_state) {
|
|
this->via2_ifr |= irq_id;
|
|
} else {
|
|
this->via2_ifr &= ~irq_id;
|
|
}
|
|
this->update_via2_irq();
|
|
}
|
|
|
|
void AMIC::ack_cpu_int(uint32_t irq_id, uint8_t irq_line_state) {
|
|
if (this->int_ctrl & CPU_INT_MODE) { // 68k interrupt emulation mode?
|
|
if (irq_line_state) {
|
|
this->dev_irq_lines |= irq_id;
|
|
} else {
|
|
this->dev_irq_lines &= ~irq_id;
|
|
}
|
|
if (!(this->int_ctrl & CPU_INT_FLAG)) {
|
|
this->int_ctrl |= CPU_INT_FLAG;
|
|
ppc_assert_int();
|
|
LOG_F(5, "AMIC: CPU INT asserted, source: %d", irq_id);
|
|
} else {
|
|
LOG_F(5, "AMIC: CPU INT already latched");
|
|
}
|
|
|
|
} else {
|
|
ABORT_F("AMIC: native interrupt mode not implemented");
|
|
}
|
|
}
|
|
|
|
void AMIC::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state) {
|
|
if (irq_id >= 0x100) { // DMA Interrupt Flags 1
|
|
irq_id = (irq_id >> 8) & 0xFFU;
|
|
if (irq_line_state)
|
|
this->dma_ifr1 |= irq_id;
|
|
else
|
|
this->dma_ifr1 &= ~irq_id;
|
|
} else { // DMA Interrupt Flags 0
|
|
irq_id &= 0xFFU;
|
|
if (irq_line_state)
|
|
this->dma_ifr0 |= irq_id;
|
|
else
|
|
this->dma_ifr0 &= ~irq_id;
|
|
}
|
|
uint8_t new_irq = (this->dma_ifr0 || this->dma_ifr1) ? 1 : 0;
|
|
if (new_irq != this->dma_irq) {
|
|
this->dma_irq = new_irq;
|
|
this->ack_cpu_int(CPU_INT_ALL_DMA, new_irq);
|
|
}
|
|
}
|
|
|
|
// ============================ Sound DMA stuff ================================
|
|
AmicSndOutDma::AmicSndOutDma() : DmaOutChannel("SndOut")
|
|
{
|
|
this->dma_out_ctrl = 0;
|
|
this->enabled = false;
|
|
}
|
|
|
|
void AmicSndOutDma::init(uint32_t buf_base, uint32_t buf_samples)
|
|
{
|
|
this->out_buf0 = buf_base + AMIC_SND_BUF0_OFFS;
|
|
this->out_buf1 = buf_base + AMIC_SND_BUF1_OFFS;
|
|
|
|
this->out_buf_len = buf_samples * 2 * 2;
|
|
|
|
this->snd_buf_num = 0;
|
|
this->cur_buf_pos = 0;
|
|
this->irq_level = 0;
|
|
}
|
|
|
|
uint8_t AmicSndOutDma::read_stat()
|
|
{
|
|
return this->dma_out_ctrl;
|
|
}
|
|
|
|
void AmicSndOutDma::update_irq() {
|
|
uint8_t new_level = !!((this->dma_out_ctrl >> 4) & this->dma_out_ctrl);
|
|
if (new_level != this->irq_level) {
|
|
this->irq_level = new_level;
|
|
TimerManager::get_instance()->add_immediate_timer([this] {
|
|
this->int_ctrl->ack_dma_int(this->irq_id, this->irq_level);
|
|
});
|
|
}
|
|
}
|
|
|
|
void AmicSndOutDma::write_dma_out_ctrl(uint8_t value)
|
|
{
|
|
// clear interrupt flags
|
|
if (value & PDM_DMA_INTS_MASK) {
|
|
this->dma_out_ctrl &= ~(value & PDM_DMA_INTS_MASK);
|
|
this->update_irq();
|
|
}
|
|
// update sound output DMA interrupt enable bits
|
|
this->dma_out_ctrl = (this->dma_out_ctrl & 0xF1U) | (value & 0x0EU);
|
|
}
|
|
|
|
DmaPullResult AmicSndOutDma::pull_data(uint32_t req_len, uint32_t *avail_len,
|
|
uint8_t **p_data)
|
|
{
|
|
*avail_len = 0;
|
|
|
|
int rem_len = this->out_buf_len - this->cur_buf_pos;
|
|
if (rem_len <= 0) {
|
|
if (!this->snd_buf_num) {
|
|
// signal buffer 0 drained
|
|
this->dma_out_ctrl |= PDM_DMA_IF0;
|
|
} else {
|
|
// signal buffer 1 drained
|
|
this->dma_out_ctrl |= PDM_DMA_IF1;
|
|
}
|
|
|
|
// generate sound out DMA interrupt if (IF0 & IE0)
|
|
// or (IF1 & IE1) or (ERR_IF & ERR_IE)
|
|
this->update_irq();
|
|
|
|
// check DMA enable flag after buffer 1 was processed
|
|
// if it's false stop delivering sound data
|
|
// this will effectively stop audio playback
|
|
if (this->snd_buf_num && !this->enabled) {
|
|
return DmaPullResult::NoMoreData;
|
|
}
|
|
|
|
this->cur_buf_pos = 0; // reset buffer position
|
|
this->snd_buf_num ^= 1; // toggle sound buffers
|
|
rem_len = this->out_buf_len; // buffer size = full buffer
|
|
}
|
|
|
|
uint32_t len = std::min((uint32_t)rem_len, req_len);
|
|
|
|
MapDmaResult res = mmu_map_dma_mem(
|
|
(this->snd_buf_num ? this->out_buf1 : this->out_buf0) + this->cur_buf_pos,
|
|
len, false);
|
|
*p_data = res.host_va;
|
|
this->cur_buf_pos += len;
|
|
*avail_len = len;
|
|
return DmaPullResult::MoreData;
|
|
}
|
|
|
|
// ============================ Floppy DMA stuff ===============================
|
|
void AmicFloppyDma::reset(const uint32_t addr_ptr)
|
|
{
|
|
this->stat &= 0x48; // clear interrupt flag, RUN and RST bits
|
|
this->addr_ptr = addr_ptr;
|
|
this->byte_count = 0;
|
|
}
|
|
|
|
void AmicFloppyDma::reinit(const uint32_t addr_ptr, const uint16_t byte_cnt)
|
|
{
|
|
this->addr_ptr = addr_ptr;
|
|
this->byte_count = byte_cnt;
|
|
}
|
|
|
|
void AmicFloppyDma::write_ctrl(uint8_t value)
|
|
{
|
|
// copy over DIR, IE and RUN bits
|
|
this->stat = (this->stat & 0x81) | (value & 0x4A);
|
|
|
|
// clear interrupt flag if requested
|
|
if (value & 0x80) {
|
|
this->stat &= 0x7F;
|
|
}
|
|
}
|
|
|
|
int AmicFloppyDma::push_data(const char* src_ptr, int len)
|
|
{
|
|
len = std::min((int)this->byte_count, len);
|
|
|
|
MapDmaResult res = mmu_map_dma_mem(this->addr_ptr, len, false);
|
|
uint8_t *p_data = res.host_va;
|
|
if (!res.is_writable) {
|
|
ABORT_F("AMIC: attempting DMA write to read-only memory");
|
|
}
|
|
std::memcpy(p_data, src_ptr, len);
|
|
|
|
this->addr_ptr += len;
|
|
this->byte_count -= len;
|
|
if (!this->byte_count) {
|
|
LOG_F(WARNING, "AMIC: DMA interrupts not implemented yet");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
DmaPullResult AmicFloppyDma::pull_data(uint32_t req_len, uint32_t *avail_len,
|
|
uint8_t **p_data)
|
|
{
|
|
return DmaPullResult::NoMoreData;
|
|
}
|
|
|
|
// ============================ SCSI DMA stuff ================================
|
|
void AmicScsiDma::reset(const uint32_t addr_ptr)
|
|
{
|
|
this->stat &= 0x48; // clear interrupt flag, RUN and RST bits
|
|
this->addr_ptr = addr_ptr;
|
|
this->byte_count = 0;
|
|
}
|
|
|
|
void AmicScsiDma::reinit(const uint32_t addr_ptr)
|
|
{
|
|
this->addr_ptr = addr_ptr;
|
|
this->byte_count = 0;
|
|
}
|
|
|
|
void AmicScsiDma::write_ctrl(uint8_t value)
|
|
{
|
|
// copy over DIR, IE and RUN bits
|
|
this->stat = (this->stat & 0x81) | (value & 0x4A);
|
|
|
|
// clear interrupt flag if requested
|
|
if (value & 0x80) {
|
|
this->stat &= 0x7F;
|
|
}
|
|
}
|
|
|
|
int AmicScsiDma::push_data(const char* src_ptr, int len)
|
|
{
|
|
MapDmaResult res = mmu_map_dma_mem(this->addr_ptr, len, false);
|
|
uint8_t *p_data = res.host_va;
|
|
std::memcpy(p_data, src_ptr, len);
|
|
|
|
this->addr_ptr += len;
|
|
|
|
return 0;
|
|
}
|
|
|
|
DmaPullResult AmicScsiDma::pull_data(uint32_t req_len, uint32_t *avail_len,
|
|
uint8_t **p_data)
|
|
{
|
|
MapDmaResult res = mmu_map_dma_mem(this->addr_ptr, req_len, false);
|
|
*p_data = res.host_va;
|
|
this->addr_ptr += req_len;
|
|
*avail_len = req_len;
|
|
return DmaPullResult::MoreData;
|
|
}
|
|
|
|
// =========================== Serial DMA stuff ===============================
|
|
void AmicSerialXmitDma::write_ctrl(const uint8_t value)
|
|
{
|
|
if (value & 1) { // RST bit set?
|
|
this->stat &= 0x7C; // clear IF, RUN and RST bits
|
|
}
|
|
|
|
// copy PAUSE to FROZEN
|
|
this->stat = (this->stat & 0xDF) | ((value & 0x10) << 1);
|
|
|
|
// copy over RELOAD, PAUSE, IE, CONT and RUN bits
|
|
this->stat = (this->stat & 0xA1) | (value & 0x5E);
|
|
|
|
// clear interrupt flag if requested
|
|
if (value & 0x80) {
|
|
this->stat &= 0x7F;
|
|
}
|
|
}
|
|
|
|
DmaPullResult AmicSerialXmitDma::pull_data(uint32_t req_len, uint32_t *avail_len,
|
|
uint8_t **p_data)
|
|
{
|
|
return DmaPullResult::NoMoreData;
|
|
};
|
|
|
|
static vector<string> Amic_Subdevices = {
|
|
"ScsiCurio", "Sc53C94", "Escc", "Mace", "ViaCuda", "Swim3"
|
|
};
|
|
|
|
static const DeviceDescription Amic_Descriptor = {
|
|
AMIC::create, Amic_Subdevices, {}
|
|
};
|
|
|
|
REGISTER_DEVICE(Amic, Amic_Descriptor);
|