mirror of
https://github.com/dingusdev/dingusppc.git
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270 lines
7.8 KiB
C++
270 lines
7.8 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** Platinum Memory Controller definitions.
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Author: Max Poliakovski
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Platinum is a single-chip memory and video subsystem controller designed
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especially for the Power Macintosh 7200 computer, code name Catalyst.
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*/
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#ifndef PLATINUM_MEMCTRL_H
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#define PLATINUM_MEMCTRL_H
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#include <devices/common/hwcomponent.h>
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#include <devices/common/mmiodevice.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <devices/video/appleramdac.h>
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#include <devices/video/displayid.h>
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#include <devices/video/videoctrl.h>
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#include <cinttypes>
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#include <memory>
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namespace Platinum {
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/** Clock source encoding in the CPUID register */
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enum {
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ClkSrc0 = 0x0000, // 33 MHz
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ClkSrc2 = 0x8000, // 20 MHz
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ClkSrc3 = 0x8040 // 31,3344 MHz
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};
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/** CPU/Bus speed encoding for ClkSrc0 */
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enum CpuSpeed0 {
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CPU_66_BUS_33 = 0,
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CPU_80_BUS_40_1 = 1,
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CPU_80_BUS_27_1 = 2,
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CPU_100_BUS_50 = 3,
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CPU_100_BUS_33 = 4,
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CPU_120_BUS_60 = 5,
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CPU_120_BUS_40 = 6,
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CPU_120_BUS_30 = 7,
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CPU_133_BUS_66 = 8,
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CPU_133_BUS_44 = 9,
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CPU_133_BUS_33 = 10,
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CPU_150_BUS_75 = 11,
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CPU_150_BUS_50 = 12,
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CPU_150_BUS_37 = 13
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};
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/** CPU/Bus speed encoding for ClkSrc2 */
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enum CpuSpeed2 {
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CPU_40_BUS_20 = 0,
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CPU_48_BUS_24 = 1,
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CPU_48_BUS_16 = 2,
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CPU_60_BUS_30 = 3,
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CPU_60_BUS_20 = 4,
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CPU_72_BUS_36 = 5,
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CPU_72_BUS_24 = 6,
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CPU_72_BUS_18 = 7,
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CPU_80_BUS_40_2 = 8,
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CPU_80_BUS_27_2 = 9,
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CPU_80_BUS_20 = 10,
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CPU_90_BUS_45 = 11,
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CPU_90_BUS_30 = 12,
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CPU_90_BUS_22 = 13
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};
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/** CPU/Bus speed encoding for ClkSrc3 */
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enum CpuSpeed3 {
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CPU_62_BUS_31 = 0,
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CPU_75_BUS_38 = 1, // actual bus frequency: 37500000 Hz
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CPU_75_BUS_25 = 2,
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CPU_94_BUS_47 = 3,
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CPU_94_BUS_31 = 4,
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CPU_113_BUS_56 = 5,
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CPU_113_BUS_38 = 6, // actual bus frequency: 37500000 Hz
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CPU_113_BUS_28 = 7,
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CPU_125_BUS_64 = 8, // actual bus frequency: 63500000 Hz
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CPU_125_BUS_42 = 9,
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CPU_125_BUS_31 = 10,
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CPU_141_BUS_72 = 11, // actual bus frequency: 71500000 Hz
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CPU_141_BUS_47 = 12,
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CPU_141_BUS_35 = 13
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};
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/** Configuration and status register offsets. */
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enum PlatinumReg : uint32_t {
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CPU_ID = 0x000,
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ASIC_REVISION = 0x010,
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ROM_TIMING = 0x020,
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CACHE_CONFIG = 0x030,
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DRAM_TIMING = 0x040,
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DRAM_REFRESH = 0x050,
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BANK_0_BASE = 0x060,
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BANK_1_BASE = 0x070,
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BANK_2_BASE = 0x080,
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BANK_3_BASE = 0x090,
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BANK_4_BASE = 0x0A0,
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BANK_5_BASE = 0x0B0,
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BANK_6_BASE = 0x0C0,
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BANK_7_BASE = 0x0D0,
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GP_SW_SCRATCH = 0x0E0,
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PCI_ADDR_MASK = 0x0F0,
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FB_BASE_ADDR = 0x100,
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ROW_WORDS = 0x120,
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CLOCK_DIVISOR = 0x130,
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FB_CONFIG_1 = 0x140,
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FB_CONFIG_2 = 0x150,
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VMEM_PAGE_MODE = 0x160,
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MON_ID_SENSE = 0x170,
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FB_RESET = 0x180,
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VRAM_REFRESH = 0x1B0,
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// Swatch timing generator registers
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SWATCH_CONFIG = 0x200,
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SWATCH_INT_MASK = 0x210,
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SWATCH_INT_STAT = 0x220,
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CLR_CURSOR_INT = 0x230,
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CLR_ANIM_INT = 0x240,
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CLR_VBL_INT = 0x250,
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CURSOR_LINE = 0x260,
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ANIMATE_LINE = 0x270,
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COUNTER_TEST = 0x280,
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SWATCH_HSERR = 0x290,
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SWATCH_HLFLN = 0x2A0,
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SWATCH_HEQ = 0x2B0,
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SWATCH_HSP = 0x2C0,
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SWATCH_HBWAY = 0x2D0,
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SWATCH_HBRST = 0x2E0,
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SWATCH_HBP = 0x2F0,
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SWATCH_HAL = 0x300,
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SWATCH_HFP = 0x310,
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SWATCH_HPIX = 0x320,
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SWATCH_VHLINE = 0x330,
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SWATCH_VSYNC = 0x340,
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SWATCH_VBPEQ = 0x350,
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SWATCH_VBP = 0x360,
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SWATCH_VAL = 0x370,
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SWATCH_VFP = 0x380,
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SWATCH_VFPEQ = 0x390,
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TIMING_ADJUST = 0x3A0,
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CURRENT_LINE = 0x3B0,
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// Iridium datapath registers
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IRIDIUM_CONFIG = 0x4A0,
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};
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#define REG_TO_INDEX(reg) ((((reg) - SWATCH_HSERR) >> 4) & 0xF)
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// FB_CONFIG_1 register bits.
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enum {
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CFG1_INTERLACE = (1 << 2), // 1 - interlaced video enabled
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CFG1_VID_ENABLE = (1 << 4), // 1 - display refresh enabled
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CFG1_FULL_BANKS = (1 << 12), // full VRAM banks (64-bit) access enable
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};
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// FB_RESET register bits.
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enum {
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VRAM_SM_RESET = (1 << 0), // VRAM state machine reset
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VREFRESH_SM_RESET = (1 << 1), // Video refresh state machine reset
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SWATCH_RESET = (1 << 2), // Swatch reset
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};
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// SWATCH_INT_MASK register bits.
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enum {
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SWATCH_INT_VBL = (1 << 0),
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SWATCH_INT_ANIM = (1 << 1),
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SWATCH_INT_CURSOR = (1 << 2)
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};
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#define DAMFB_VERSION_PLATINUM 6 // DAMFB cell version in the Platinum ASIC
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#define IRIDIUM_VENDOR_VLSI 0 // Vendor ID for the Iridium ASIC => VLSI
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constexpr auto VRAM_REGION_BASE = 0xF1000000UL;
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constexpr auto PLATINUM_IOREG_BASE = 0xF8000000UL;
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}; // namespace Platinum
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class PlatinumCtrl : public MemCtrlBase, public VideoCtrlBase, public MMIODevice {
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public:
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PlatinumCtrl();
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~PlatinumCtrl() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<PlatinumCtrl>(new PlatinumCtrl());
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}
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// HWComponent methods
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int device_postinit();
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// MMIODevice methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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void insert_ram_dimm(int slot_num, uint32_t capacity);
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void map_phys_ram();
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protected:
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void enable_display();
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void enable_cursor_int();
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void update_irq(uint8_t irq_line_state, uint8_t irq_mask);
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private:
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uint32_t cpu_id;
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uint8_t cpu_type; // 0 - MPC601, 1 - 603/604 CPU
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// memory controller state
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uint32_t rom_timing = 0;
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uint32_t dram_timing = 0xEFF;
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uint32_t dram_refresh = 0x1F4;
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uint32_t bank_base[8] = {};
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uint32_t bank_size[8] = {};
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// frame buffer controller state
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uint32_t fb_addr = Platinum::VRAM_REGION_BASE;
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uint32_t fb_offset = 0;
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uint32_t fb_config_1 = 0x1F00;
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uint32_t fb_config_2 = 0x1FFF;
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uint32_t clock_divisor = 0;
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uint32_t row_words = 0;
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uint32_t fb_reset = 7;
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int reset_step = 0;
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uint32_t fb_test = DAMFB_VERSION_PLATINUM << 9;
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uint32_t vram_refresh = 0x1F4;
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uint32_t vram_size = 0;
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uint32_t iridium_cfg = (IRIDIUM_VENDOR_VLSI << 24) | 1; // big-endian bus
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uint8_t vram_megs = 0;
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uint8_t half_bank = 0;
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uint8_t half_access = 0;
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uint8_t vmem_fp_mode = 0;
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uint8_t mon_sense = 0;
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// video timing generator (Swatch) state
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uint32_t swatch_config = 0xFFD;
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uint32_t swatch_params[17] = {};
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uint32_t timing_adjust = 0;
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// interrupt related state
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uint32_t swatch_int_mask = 0;
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uint32_t swatch_int_stat = 0;
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uint32_t cursor_line = 0;
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uint32_t cursor_task_id = 0;
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std::unique_ptr<uint8_t[]> vram_ptr = nullptr;
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std::unique_ptr<DisplayID> display_id = nullptr;
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std::unique_ptr<AppleRamdac> dacula = nullptr;
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};
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#endif // PLATINUM_MEMCTRL_H
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