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https://github.com/dingusdev/dingusppc.git
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dingusdev
211 lines
7.8 KiB
C++
211 lines
7.8 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-26 The DingusPPC Development Team
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(See CREDITS.MD for more details)
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(You may also contact divingkxt or powermax2286 on Discord)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MPC106 (Grackle) definitions.
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Grackle IC is a combined memory and PCI controller manufactured by Motorola.
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It's the central device in the Gossamer architecture.
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Manual: https://www.nxp.com/docs/en/reference-manual/MPC106UM.pdf
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This code emulates as much functionality as needed to run Power Mac Beige G3.
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This implies that
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- we only support address map B
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- our virtual device reports revision 4.0 as expected by machine firmware
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*/
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#ifndef MPC106_H
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#define MPC106_H
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#include <devices/common/pci/pcidevice.h>
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#include <devices/common/pci/pcihost.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <machines/machinebase.h>
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#include <cinttypes>
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#include <memory>
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class InterruptCtrl;
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/** Grackle configuration space registers. */
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enum GrackleReg : uint32_t {
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CFG10 = 0x40, // bus # + subordinate bus # + disconnect counter
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PMCR1 = 0x70, // power management config 1
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MSAR1 = 0x80, // memory starting address 1
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MSAR2 = 0x84, // memory starting address 2
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EMSAR1 = 0x88, // extended memory starting address 1
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EMSAR2 = 0x8C, // extended memory starting address 2
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MEAR1 = 0x90, // memory ending address 1
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MEAR2 = 0x94, // memory ending address 2
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EMEAR1 = 0x98, // extended memory ending address 1
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EMEAR2 = 0x9C, // extended memory ending address 2
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MBER = 0xA0, // memory bank enable
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PICR1 = 0xA8, // processor interface configuration 1
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PICR2 = 0xAC, // processor interface configuration 2
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MCCR1 = 0xF0, // memory control configuration 1
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MCCR2 = 0xF4, // memory control configuration 2
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MCCR3 = 0xF8, // memory control configuration 3
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MCCR4 = 0xFC // memory control configuration 4
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};
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/* PICR1 bit definitions. */
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enum {
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CF_L2_MP_SHIFT = 0,
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CF_L2_MP_MASK = 3 << CF_L2_MP_SHIFT,
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SPECULATIVE_PCI_READS = 1 << 2,
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CF_APARK = 1 << 3,
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CF_LOOP_SNOOP = 1 << 4,
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LE_MODE = 1 << 5,
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ST_GATH_EN = 1 << 6,
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NO_PORT_REGS = 1 << 7,
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CF_EXTERNAL_L2 = 1 << 8,
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CF_DPARK = 1 << 9,
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TEA_EN = 1 << 10, // enabled during ROM flashing
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MCP_EN = 1 << 11,
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FLASH_WR_EN = 1 << 12, // enabled during ROM flashing, disabled after ROM flashing
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CF_LBA_EN = 1 << 13,
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CF_MP_ID_SHIFT = 14,
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CF_MP_ID_MASK = 3 << CF_MP_ID_SHIFT,
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ADDRESS_MAP = 1 << 16,
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PROC_TYPE_SHIFT = 17,
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PROC_TYPE_MASK = 3 << PROC_TYPE_SHIFT,
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XIO_MODE = 1 << 19,
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RCS0 = 1 << 20,
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CF_CACHE_1G = 1 << 21,
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CF_BREAD_WS_SHIFT = 22,
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CF_BREAD_WS_MASK = 3 << CF_BREAD_WS_SHIFT,
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CF_CBA_MASK_SHIFT = 24,
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CF_CBA_MASK_MASK = 0xff << CF_CBA_MASK_SHIFT,
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};
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/* PICR2 bit definitions. */
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enum {
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CF_WDATA = 0,
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CF_DOE = 1,
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CF_APHASE_WS_SHIFT = 2,
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CF_APHASE_WS_MASK = 3 << CF_APHASE_WS_SHIFT,
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CF_L2_SIZE_SHIFT = 4,
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CF_L2_SIZE_MASK = 3 << CF_L2_SIZE_SHIFT,
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CF_TOE_WIDTH = 6,
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CF_FAST_CASTOUT = 7,
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CF_TWO_BANKS = 8,
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CF_L2_HIT_DELAY_SHIFT = 9,
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CF_L2_HIT_DELAY_MASK = 3 << CF_L2_HIT_DELAY_SHIFT,
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CF_RWITM_FILL = 11,
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CF_INV_MODE = 12,
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CF_HOLD = 13,
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CF_ADDR_ONLY_DISABLE = 14,
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// RESERVED = 15,
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CF_HIT_HIGH = 16,
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CF_MOD_HIGH = 17,
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CF_SNOOP_WS_SHIFT = 18,
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CF_SNOOP_WS_MASK = 3 << CF_SNOOP_WS_SHIFT,
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CF_WMODE_SHIFT = 20,
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CF_WMODE_MASK = 3 << CF_WMODE_SHIFT,
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CF_DATA_RAM_TYPE_SHIFT = 22,
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CF_DATA_RAM_TYPE_MASK = 3 << CF_DATA_RAM_TYPE_SHIFT,
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CF_FAST_L2_MODE = 24,
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FLASH_WR_LOCKOUT = 25, // Programmer Mode changes this to 0 which allows flash writing.
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CF_FF0_LOCAL = 26,
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NO_SNOOP_EN = 27,
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CF_FLUSH_L2 = 28,
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NO_SERIAL_CFG = 29,
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L2_EN = 30,
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L2_UPDATE_EN = 31,
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};
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/* MCCR1 bit definitions. */
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enum {
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BANK_0_ROW_SHIFT = 0,
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BANK_0_ROW_MASK = 3 << BANK_0_ROW_SHIFT,
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BANK_1_ROW_SHIFT = 2,
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BANK_1_ROW_MASK = 3 << BANK_1_ROW_SHIFT,
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BANK_2_ROW_SHIFT = 4,
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BANK_2_ROW_MASK = 3 << BANK_2_ROW_SHIFT,
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BANK_3_ROW_SHIFT = 6,
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BANK_3_ROW_MASK = 3 << BANK_3_ROW_SHIFT,
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BANK_4_ROW_SHIFT = 8,
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BANK_4_ROW_MASK = 3 << BANK_4_ROW_SHIFT,
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BANK_5_ROW_SHIFT = 10,
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BANK_5_ROW_MASK = 3 << BANK_5_ROW_SHIFT,
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BANK_6_ROW_SHIFT = 12,
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BANK_6_ROW_MASK = 3 << BANK_6_ROW_SHIFT,
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BANK_7_ROW_SHIFT = 14,
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BANK_7_ROW_MASK = 3 << BANK_7_ROW_SHIFT,
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PCKEN = 1 << 16,
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RAM_TYPE = 1 << 17,
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SREN = 1 << 18,
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MEMGO = 1 << 19,
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BURST = 1 << 20,
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_8N64 = 1 << 21, // 1 = the MPC106 is configured for an 8-bit data path for ROM bank 0 rather than 64-bit
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_501_MODE = 1 << 22,
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ROMFAL_SHIFT = 23,
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ROMFAL_MASK = 31 << ROMFAL_SHIFT,
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ROMNAL_SHIFT = 28,
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ROMNAL_MASK = 15 << ROMNAL_SHIFT,
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};
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class MPC106 : public MemCtrlBase, public PCIDevice, public PCIHost {
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public:
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MPC106();
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~MPC106() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<MPC106>(new MPC106());
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}
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size) override;
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) override;
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int device_postinit() override;
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protected:
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/* my own PCI configuration registers access */
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uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details) override;
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void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details) override;
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void setup_ram(void);
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private:
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inline void cfg_setup(uint32_t offset, int size, int &bus_num, int &dev_num,
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int &fun_num, uint8_t ®_offs, AccessDetails &details,
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PCIBase *&device);
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uint32_t config_addr;
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uint16_t pmcr1 = 0; // power management config 1
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uint8_t pmcr2 = 0; // power management config 2
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uint8_t odcr = 0xCD; // output driver control
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uint32_t picr1 = 0xFF100010; // ROM on CPU bus, address map B, CPU type = MPC601
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uint32_t picr2 = 0x000C060C;
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uint32_t mccr1 = 0xFF820000; // 64bit ROM bus
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uint32_t mccr2 = 3;
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uint32_t mccr3 = 0;
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uint32_t mccr4 = 0x00100000;
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uint32_t mem_start[2] = {};
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uint32_t ext_mem_start[2] = {};
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uint32_t mem_end[2] = {};
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uint32_t ext_mem_end[2] = {};
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uint8_t mem_bank_en = 0;
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};
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#endif // MPC106_H
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