mirror of
https://github.com/dingusdev/dingusppc.git
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117 lines
3.4 KiB
C++
117 lines
3.4 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Media Access Controller for Ethernet (MACE) definitions. */
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#ifndef MACE_H
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#define MACE_H
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#include <devices/common/dmacore.h>
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#include <devices/common/hwcomponent.h>
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#include <cinttypes>
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#include <memory>
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/** Known MACE chip IDs. */
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#define MACE_ID_REV_B0 0x0940 // Darwin-0.3 source
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#define MACE_ID_REV_A2 0x0941 // Darwin-0.3 source & Curio datasheet
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/** MACE registers offsets. */
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// Refer to the Am79C940 datasheet for details
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namespace MaceEnet {
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enum MaceReg : uint8_t {
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Rcv_FIFO = 0,
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Xmit_FIFO = 1,
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Xmit_Frame_Ctrl = 2,
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Xmit_Frame_Stat = 3,
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Xmit_Retry_Cnt = 4,
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Rcv_Frame_Ctrl = 5,
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Rcv_Frame_Stat = 6,
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FIFO_Frame_Cnt = 7,
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Interrupt = 8,
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Interrupt_Mask = 9,
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Poll = 10,
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BIU_Config_Ctrl = 11,
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FIFO_Config = 12,
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MAC_Config_Ctrl = 13,
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PLS_Config_Ctrl = 14,
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PHY_Config_Ctrl = 15,
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Chip_ID_Lo = 16,
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Chip_ID_Hi = 17,
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Int_Addr_Config = 18,
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Log_Addr_Flt = 20,
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Phys_Addr = 21,
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Missed_Pkt_Cnt = 24,
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Runt_Pkt_Cnt = 26, // not used in Macintosh?
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Rcv_Collis_Cnt = 27, // not used in Macintosh?
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User_Test = 29,
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Rsrvd_Test_1 = 30, // not used in Macintosh?
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Rsrvd_Test_2 = 31, // not used in Macintosh?
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};
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/** Bit definitions for BIU_Config_Ctrl register. */
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enum {
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BIU_SWRST = 1 << 0,
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};
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/** Bit definitions for the internal configuration register. */
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enum {
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IAC_LOGADDR = 1 << 1,
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IAC_PHYADDR = 1 << 2,
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IAC_ADDRCHG = 1 << 7
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};
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}; // namespace MaceEnet
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class MaceController : public DmaDevice, public HWComponent {
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public:
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MaceController(uint16_t id) {
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this->chip_id = id;
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this->set_name("MACE");
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this->supports_types(HWCompType::MMIO_DEV | HWCompType::ETHER_MAC);
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};
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~MaceController() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<MaceController>(new MaceController(MACE_ID_REV_A2));
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}
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// MACE registers access
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uint8_t read(uint8_t reg_offset);
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void write(uint8_t reg_offset, uint8_t value);
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private:
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uint16_t chip_id; // per-instance MACE Chip ID
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uint8_t addr_cfg = 0;
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uint8_t addr_ptr = 0;
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uint8_t rcv_fc = 1;
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uint8_t biu_ctrl = 0;
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uint8_t mac_cfg = 0;
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uint64_t phys_addr = 0;
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uint64_t log_addr = 0;
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// interrupt stuff
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uint8_t int_stat = 0;
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uint8_t int_mask = 0;
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};
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#endif // MACE_H
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