mirror of
https://github.com/dingusdev/dingusppc.git
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141 lines
3.7 KiB
C++
141 lines
3.7 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file ATA interface definitions. */
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#ifndef ATA_INTERFACE_H
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#define ATA_INTERFACE_H
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#include <cinttypes>
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namespace ata_interface {
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/** ATA register offsets. */
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enum IDE_Reg : int {
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DATA = 0x0,
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ERROR = 0x1, // error (read)
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FEATURES = 0x1, // features (write)
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SEC_COUNT = 0x2, // sector count
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SEC_NUM = 0x3, // sector number
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CYL_LOW = 0x4, // cylinder low
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CYL_HIGH = 0x5, // cylinder high
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DEVICE_HEAD = 0x6, // device/head
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STATUS = 0x7, // status (read)
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COMMAND = 0x7, // command (write)
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ALT_STATUS = 0x16, // alt status (read)
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DEV_CTRL = 0x16, // device control (write)
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TIME_CONFIG = 0x20
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};
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/** Status register bits. */
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enum IDE_Status : int {
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ERR = 0x1,
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IDX = 0x2,
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CORR = 0x4,
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DRQ = 0x8,
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DSC = 0x10,
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DWF = 0x20,
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DRDY = 0x40,
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BSY = 0x80
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};
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/** Error register bits. */
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enum IDE_Error : int {
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ANMF = 0x1,
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TK0NF = 0x2,
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ABRT = 0x4,
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MCR = 0x8,
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IDNF = 0x10,
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MC = 0x20,
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UNC = 0x40,
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BBK = 0x80
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};
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/** Bit definition for the device control register. */
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enum {
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ATA_CTRL_nIEN = 1 << 1,
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ATA_CTRL_SRST = 1 << 2,
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};
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/* ATA commands. */
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enum IDE_Cmd : int {
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NOP = 0x00,
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RESET_ATAPI = 0x08,
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RECALIBRATE = 0x10,
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READ_SECTOR = 0x20,
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READ_SECTOR_NR = 0x21,
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READ_LONG = 0x22,
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READ_SECTOR_EXT = 0x24,
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WRITE_SECTOR = 0x30,
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WRITE_SECTOR_NR = 0x21,
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WRITE_LONG = 0x32,
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READ_VERIFY = 0x40,
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FORMAT_TRACKS = 0x50,
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IDE_SEEK = 0x70,
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DIAGNOSTICS = 0x90,
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INIT_DEV_PARAM = 0x91,
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PACKET = 0xA0,
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IDFY_PKT_DEV = 0xA1,
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READ_MULTIPLE = 0xC4,
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WRITE_MULTIPLE = 0xC5,
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READ_DMA = 0xC8,
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WRITE_DMA = 0xCA,
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WRITE_BUFFER_DMA = 0xE9,
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READ_BUFFER_DMA = 0xEB,
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IDENTIFY_DEVICE = 0xEC,
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};
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}; // namespace ata_interface
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/** Interface for ATA devices. */
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class AtaInterface {
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public:
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AtaInterface() = default;
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virtual ~AtaInterface() = default;
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virtual uint16_t read(const uint8_t reg_addr) = 0;
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virtual void write(const uint8_t reg_addr, const uint16_t val) = 0;
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virtual int get_device_id() = 0;
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};
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/** Dummy ATA device. */
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class AtaNullDevice : public AtaInterface {
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public:
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AtaNullDevice() = default;
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~AtaNullDevice() = default;
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uint16_t read(const uint8_t reg_addr) {
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// return all one's except DD7 if no device is present
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// DD7 corresponds to the BSY bit of the status register
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// The host should have a pull-down resistor on DD7
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// to prevent the software from waiting for a long time
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// for empty slots
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return 0xFF7FU;
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};
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void write(const uint8_t reg_addr, const uint16_t val) {};
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// invalid device ID means no real device is present
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int get_device_id() { return -1; };
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};
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#endif // ATA_INTERFACE_H
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