mirror of
https://github.com/dingusdev/dingusppc.git
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564c43c907
Replace it wth an explicit opcode parameter that is passed around. That is both slightly easier to reason about (to trace where it comes from) and slightly faster, since it can be read from a register. On my machine takes booting to "Welcome to Macintosh" being output in a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5 runs, measured using deterministic mode and looking at when execution reaches PC 0x90004a88).
671 lines
22 KiB
C++
671 lines
22 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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// The Power-specific opcodes for the processor - ppcopcodes.cpp
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// Any shared opcodes are in ppcopcodes.cpp
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#include "ppcemu.h"
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#include "ppcmacros.h"
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#include "ppcmmu.h"
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#include <stdint.h>
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/** mask generator for rotate and shift instructions (§ 4.2.1.4 PowerpC PEM) */
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static inline uint32_t power_rot_mask(unsigned rot_mb, unsigned rot_me) {
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uint32_t m1 = 0xFFFFFFFFU >> rot_mb;
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uint32_t m2 = 0xFFFFFFFFU << (31 - rot_me);
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return ((rot_mb <= rot_me) ? m2 & m1 : m1 | m2);
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}
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template <field_rc rec, field_ov ov>
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void dppc_interpreter::power_abs(uint32_t opcode) {
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uint32_t ppc_result_d;
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ppc_grab_regsda(opcode);
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if (ppc_result_a == 0x80000000) {
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ppc_result_d = ppc_result_a;
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if (ov)
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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} else {
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ppc_result_d = (int32_t(ppc_result_a) < 0) ? -ppc_result_a : ppc_result_a;
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if (ov)
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ppc_state.spr[SPR::XER] &= ~XER::OV;
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}
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if (rec)
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ppc_changecrf0(ppc_result_d);
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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}
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template void dppc_interpreter::power_abs<RC0, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_abs<RC0, OV1>(uint32_t opcode);
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template void dppc_interpreter::power_abs<RC1, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_abs<RC1, OV1>(uint32_t opcode);
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void dppc_interpreter::power_clcs(uint32_t opcode) {
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uint32_t ppc_result_d;
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ppc_grab_da(opcode);
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switch (reg_a) {
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case 12: //instruction cache line size
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case 13: //data cache line size
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case 14: //minimum line size
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case 15: //maximum line size
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default: ppc_result_d = is_601 ? 64 : 32; break;
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case 7:
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case 23: ppc_result_d = is_601 ? 64 : 0; break;
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case 8:
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case 9:
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case 24:
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case 25: ppc_result_d = is_601 ? 64 : 4; break;
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case 10:
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case 11:
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case 26:
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case 27: ppc_result_d = is_601 ? 64 : 0x4000; break;
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}
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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}
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template <field_rc rec, field_ov ov>
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void dppc_interpreter::power_div(uint32_t opcode) {
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uint32_t ppc_result_d;
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ppc_grab_regsdab(opcode);
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int64_t dividend = (uint64_t(ppc_result_a) << 32) | ppc_state.spr[SPR::MQ];
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int32_t divisor = ppc_result_b;
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int64_t quotient;
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int32_t remainder;
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if (dividend == -0x80000000 && divisor == -1) {
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remainder = 0;
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ppc_result_d = 0x80000000U; // -2^31 aka INT32_MIN
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if (ov)
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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} else if (!divisor) {
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remainder = 0;
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ppc_result_d = 0x80000000U; // -2^31 aka INT32_MIN
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if (ov)
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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} else {
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quotient = dividend / divisor;
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remainder = dividend % divisor;
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ppc_result_d = uint32_t(quotient);
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if (ov) {
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if (((quotient >> 31) + 1) & ~1) {
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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} else {
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ppc_state.spr[SPR::XER] &= ~XER::OV;
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}
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}
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}
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if (rec)
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ppc_changecrf0(remainder);
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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ppc_state.spr[SPR::MQ] = remainder;
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}
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template void dppc_interpreter::power_div<RC0, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_div<RC0, OV1>(uint32_t opcode);
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template void dppc_interpreter::power_div<RC1, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_div<RC1, OV1>(uint32_t opcode);
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template <field_rc rec, field_ov ov>
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void dppc_interpreter::power_divs(uint32_t opcode) {
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uint32_t ppc_result_d;
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int32_t remainder;
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ppc_grab_regsdab(opcode);
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if (!ppc_result_b) { // handle the "anything / 0" case
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ppc_result_d = -1;
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remainder = ppc_result_a;
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if (ov)
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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} else if (ppc_result_a == 0x80000000U && ppc_result_b == 0xFFFFFFFFU) {
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ppc_result_d = 0x80000000U;
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remainder = 0;
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if (ov)
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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} else { // normal signed devision
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ppc_result_d = int32_t(ppc_result_a) / int32_t(ppc_result_b);
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remainder = (int32_t(ppc_result_a) % int32_t(ppc_result_b));
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if (ov)
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ppc_state.spr[SPR::XER] &= ~XER::OV;
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}
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if (rec)
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ppc_changecrf0(remainder);
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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ppc_state.spr[SPR::MQ] = remainder;
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}
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template void dppc_interpreter::power_divs<RC0, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_divs<RC0, OV1>(uint32_t opcode);
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template void dppc_interpreter::power_divs<RC1, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_divs<RC1, OV1>(uint32_t opcode);
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template <field_rc rec, field_ov ov>
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void dppc_interpreter::power_doz(uint32_t opcode) {
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ppc_grab_regsdab(opcode);
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uint32_t ppc_result_d = (int32_t(ppc_result_a) < int32_t(ppc_result_b)) ?
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ppc_result_b - ppc_result_a : 0;
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if (ov) {
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if (int32_t(ppc_result_d) < 0) {
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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} else {
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ppc_state.spr[SPR::XER] &= ~XER::OV;
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}
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}
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if (rec)
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ppc_changecrf0(ppc_result_d);
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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}
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template void dppc_interpreter::power_doz<RC0, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_doz<RC0, OV1>(uint32_t opcode);
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template void dppc_interpreter::power_doz<RC1, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_doz<RC1, OV1>(uint32_t opcode);
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void dppc_interpreter::power_dozi(uint32_t opcode) {
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uint32_t ppc_result_d;
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ppc_grab_regsdasimm(opcode);
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if (((int32_t)ppc_result_a) > simm) {
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ppc_result_d = 0;
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} else {
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ppc_result_d = simm - ppc_result_a;
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}
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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}
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template <field_rc rec>
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void dppc_interpreter::power_lscbx(uint32_t opcode) {
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ppc_grab_regsdab(opcode);
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uint32_t ea = ppc_result_b + (reg_a ? ppc_result_a : 0);
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uint32_t bytes_to_load = (ppc_state.spr[SPR::XER] & 0x7F);
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uint32_t bytes_remaining = bytes_to_load;
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uint8_t matching_byte = (uint8_t)(ppc_state.spr[SPR::XER] >> 8);
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uint32_t ppc_result_d = 0;
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bool is_match = false;
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// for storing each byte
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uint8_t shift_amount = 24;
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while (bytes_remaining > 0) {
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uint8_t return_value = mmu_read_vmem<uint8_t>(opcode, ea);
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ppc_result_d |= return_value << shift_amount;
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if (!shift_amount) {
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if (reg_d != reg_a && reg_d != reg_b)
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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reg_d = (reg_d + 1) & 0x1F;
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ppc_result_d = 0;
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shift_amount = 24;
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} else {
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shift_amount -= 8;
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}
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ea++;
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bytes_remaining--;
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if (return_value == matching_byte) {
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is_match = true;
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break;
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}
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}
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// store partially loaded register if any
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if (shift_amount != 24 && reg_d != reg_a && reg_d != reg_b)
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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ppc_state.spr[SPR::XER] = (ppc_state.spr[SPR::XER] & ~0x7F) | (bytes_to_load - bytes_remaining);
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if (rec) {
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ppc_state.cr =
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(ppc_state.cr & 0x0FFFFFFFUL) |
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(is_match ? CRx_bit::CR_EQ : 0) |
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((ppc_state.spr[SPR::XER] & XER::SO) >> 3);
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}
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}
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template void dppc_interpreter::power_lscbx<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_lscbx<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_maskg(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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uint32_t mask_start = ppc_result_d & 0x1F;
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uint32_t mask_end = ppc_result_b & 0x1F;
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uint32_t insert_mask = 0;
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if (mask_start < (mask_end + 1)) {
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insert_mask = power_rot_mask(mask_start, mask_end);
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}
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else if (mask_start == (mask_end + 1)) {
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insert_mask = 0xFFFFFFFF;
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}
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else {
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insert_mask = ~(power_rot_mask(mask_end + 1, mask_start - 1));
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}
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ppc_result_a = insert_mask;
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_maskg<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_maskg<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_maskir(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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ppc_result_a = (ppc_result_a & ~ppc_result_b) | (ppc_result_d & ppc_result_b);
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_maskir<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_maskir<RC1>(uint32_t opcode);
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template <field_rc rec, field_ov ov>
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void dppc_interpreter::power_mul(uint32_t opcode) {
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ppc_grab_regsdab(opcode);
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int64_t product = int64_t(int32_t(ppc_result_a)) * int32_t(ppc_result_b);
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uint32_t ppc_result_d = uint32_t(uint64_t(product) >> 32);
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ppc_state.spr[SPR::MQ] = uint32_t(product);
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if (ov) {
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if (uint64_t(product >> 31) + 1 & ~1) {
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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} else {
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ppc_state.spr[SPR::XER] &= ~XER::OV;
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}
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}
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if (rec)
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ppc_changecrf0(uint32_t(product));
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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}
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template void dppc_interpreter::power_mul<RC0, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_mul<RC0, OV1>(uint32_t opcode);
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template void dppc_interpreter::power_mul<RC1, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_mul<RC1, OV1>(uint32_t opcode);
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template <field_rc rec, field_ov ov>
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void dppc_interpreter::power_nabs(uint32_t opcode) {
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ppc_grab_regsda(opcode);
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uint32_t ppc_result_d = (int32_t(ppc_result_a) < 0) ? ppc_result_a : -ppc_result_a;
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if (ov)
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ppc_state.spr[SPR::XER] &= ~XER::OV;
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if (rec)
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ppc_changecrf0(ppc_result_d);
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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}
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template void dppc_interpreter::power_nabs<RC0, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_nabs<RC0, OV1>(uint32_t opcode);
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template void dppc_interpreter::power_nabs<RC1, OV0>(uint32_t opcode);
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template void dppc_interpreter::power_nabs<RC1, OV1>(uint32_t opcode);
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void dppc_interpreter::power_rlmi(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_mb = (opcode >> 6) & 0x1F;
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unsigned rot_me = (opcode >> 1) & 0x1F;
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unsigned rot_sh = ppc_result_b & 0x1F;
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uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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uint32_t mask = power_rot_mask(rot_mb, rot_me);
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ppc_result_a = ((r & mask) | (ppc_result_a & ~mask));
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if ((opcode & 0x01) == 1)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template <field_rc rec>
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void dppc_interpreter::power_rrib(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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if (int32_t(ppc_result_d) < 0) {
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ppc_result_a |= (0x80000000U >> rot_sh);
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} else {
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ppc_result_a &= ~(0x80000000U >> rot_sh);
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}
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_rrib<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_rrib<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sle(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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ppc_result_a = ppc_result_d << rot_sh;
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ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sle<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sle<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sleq(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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uint32_t mask = power_rot_mask(0, 31 - rot_sh);
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ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
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ppc_state.spr[SPR::MQ] = r;
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sleq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sleq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sliq(uint32_t opcode) {
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ppc_grab_regssash(opcode);
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ppc_result_a = ppc_result_d << rot_sh;
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ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sliq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sliq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_slliq(uint32_t opcode) {
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ppc_grab_regssash(opcode);
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uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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uint32_t mask = power_rot_mask(0, 31 - rot_sh);
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ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
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ppc_state.spr[SPR::MQ] = r;
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_slliq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_slliq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sllq(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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if (ppc_result_b & 0x20) {
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ppc_result_a = ppc_state.spr[SPR::MQ] & (-1U << rot_sh);
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} else {
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ppc_result_a = ((ppc_result_d << rot_sh) | (ppc_state.spr[SPR::MQ] & ((1 << rot_sh) - 1)));
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}
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sllq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sllq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_slq(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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if (ppc_result_b & 0x20) {
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ppc_result_a = 0;
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} else {
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ppc_result_a = ppc_result_d << rot_sh;
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}
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_slq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_slq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sraiq(uint32_t opcode) {
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ppc_grab_regssash(opcode);
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uint32_t mask = (1 << rot_sh) - 1;
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ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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if ((int32_t(ppc_result_d) < 0) && (ppc_result_d & mask)) {
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ppc_state.spr[SPR::XER] |= XER::CA;
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} else {
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ppc_state.spr[SPR::XER] &= ~XER::CA;
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}
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sraiq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sraiq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sraq(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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uint32_t mask = (ppc_result_b & 0x20) ? -1 : (1 << rot_sh) - 1;
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ppc_result_a = (int32_t)ppc_result_d >> ((ppc_result_b & 0x20) ? 31 : rot_sh);
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ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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if ((int32_t(ppc_result_d) < 0) && (ppc_result_d & mask)) {
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ppc_state.spr[SPR::XER] |= XER::CA;
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} else {
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ppc_state.spr[SPR::XER] &= ~XER::CA;
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}
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sraq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sraq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sre(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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ppc_result_a = ppc_result_d >> rot_sh;
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sre<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sre<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_srea(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
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uint32_t r = ((ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh)));
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uint32_t mask = -1U >> rot_sh;
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if ((int32_t(ppc_result_d) < 0) && (r & ~mask)) {
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ppc_state.spr[SPR::XER] |= XER::CA;
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} else {
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ppc_state.spr[SPR::XER] &= ~XER::CA;
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}
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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ppc_state.spr[SPR::MQ] = r;
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}
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template void dppc_interpreter::power_srea<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_srea<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sreq(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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uint32_t mask = -1U >> rot_sh;
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ppc_result_a = (ppc_result_d >> rot_sh) | (ppc_state.spr[SPR::MQ] & ~mask);
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sreq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sreq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_sriq(uint32_t opcode) {
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ppc_grab_regssash(opcode);
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ppc_result_a = ppc_result_d >> rot_sh;
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_sriq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_sriq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_srliq(uint32_t opcode) {
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ppc_grab_regssash(opcode);
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uint32_t r = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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unsigned mask = power_rot_mask(rot_sh, 31);
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ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
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ppc_state.spr[SPR::MQ] = r;
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_srliq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_srliq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_srlq(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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uint32_t r = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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unsigned mask = power_rot_mask(rot_sh, 31);
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if (ppc_result_b & 0x20) {
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ppc_result_a = (ppc_state.spr[SPR::MQ] & mask);
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} else {
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ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
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}
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_srlq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_srlq<RC1>(uint32_t opcode);
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template <field_rc rec>
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void dppc_interpreter::power_srq(uint32_t opcode) {
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ppc_grab_regssab(opcode);
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unsigned rot_sh = ppc_result_b & 0x1F;
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if (ppc_result_b & 0x20) {
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ppc_result_a = 0;
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} else {
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ppc_result_a = ppc_result_d >> rot_sh;
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}
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_store_iresult_reg(reg_a, ppc_result_a);
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}
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template void dppc_interpreter::power_srq<RC0>(uint32_t opcode);
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template void dppc_interpreter::power_srq<RC1>(uint32_t opcode);
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