mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-12-27 00:29:18 +00:00
1009 lines
31 KiB
C++
1009 lines
31 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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// The floating point opcodes for the processor - ppcfpopcodes.cpp
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#include "ppcemu.h"
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#include "ppcmmu.h"
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#include <stdlib.h>
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#include <cfenv>
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#include <cinttypes>
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#include <cmath>
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#include <cfloat>
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// Used for FP calcs
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uint64_t ppc_result64_d;
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double ppc_dblresult64_d;
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// Storage and register retrieval functions for the floating point functions.
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#define GET_FPR(reg) ppc_state.fpr[(reg)].dbl64_r
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double fp_return_double(uint32_t reg) {
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return ppc_state.fpr[reg].dbl64_r;
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}
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uint64_t fp_return_uint64(uint32_t reg) {
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return ppc_state.fpr[reg].int64_r;
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}
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#define ppc_store_sfpresult_int(reg) \
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ppc_state.fpr[(reg)].int64_r = ppc_result64_d;
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#define ppc_store_sfpresult_flt(reg) \
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ppc_state.fpr[(reg)].dbl64_r = ppc_dblresult64_d;
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#define ppc_store_dfpresult_int(reg) \
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ppc_state.fpr[(reg)].int64_r = ppc_result64_d;
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#define ppc_store_dfpresult_flt(reg) \
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ppc_state.fpr[(reg)].dbl64_r = ppc_dblresult64_d;
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#define ppc_grab_regsfpdb() \
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int reg_d = (ppc_cur_instruction >> 21) & 31; \
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int reg_b = (ppc_cur_instruction >> 11) & 31;
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#define ppc_grab_regsfpdiab() \
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int reg_d = (ppc_cur_instruction >> 21) & 31; \
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int reg_a = (ppc_cur_instruction >> 16) & 31; \
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int reg_b = (ppc_cur_instruction >> 11) & 31; \
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uint32_t val_reg_a = ppc_state.gpr[reg_a]; \
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uint32_t val_reg_b = ppc_state.gpr[reg_b];
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#define ppc_grab_regsfpdia() \
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int reg_d = (ppc_cur_instruction >> 21) & 31; \
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int reg_a = (ppc_cur_instruction >> 16) & 31; \
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uint32_t val_reg_a = ppc_state.gpr[reg_a];
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#define ppc_grab_regsfpsia() \
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int reg_s = (ppc_cur_instruction >> 21) & 31; \
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int reg_a = (ppc_cur_instruction >> 16) & 31; \
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uint32_t val_reg_a = ppc_state.gpr[reg_a];
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#define ppc_grab_regsfpsiab() \
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int reg_s = (ppc_cur_instruction >> 21) & 31; \
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int reg_a = (ppc_cur_instruction >> 16) & 31; \
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int reg_b = (ppc_cur_instruction >> 11) & 31; \
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uint32_t val_reg_a = ppc_state.gpr[reg_a]; \
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uint32_t val_reg_b = ppc_state.gpr[reg_b];
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#define ppc_grab_regsfpsab() \
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int reg_a = (ppc_cur_instruction >> 16) & 31; \
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int reg_b = (ppc_cur_instruction >> 11) & 31; \
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int crf_d = (ppc_cur_instruction >> 21) & 0x1C; \
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double db_test_a = GET_FPR(reg_a); \
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double db_test_b = GET_FPR(reg_b);
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#define ppc_grab_regsfpdab() \
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int reg_d = (ppc_cur_instruction >> 21) & 31; \
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int reg_a = (ppc_cur_instruction >> 16) & 31; \
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int reg_b = (ppc_cur_instruction >> 11) & 31; \
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double val_reg_a = GET_FPR(reg_a); \
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double val_reg_b = GET_FPR(reg_b);
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#define ppc_grab_regsfpdac() \
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int reg_d = (ppc_cur_instruction >> 21) & 31; \
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int reg_a = (ppc_cur_instruction >> 16) & 31; \
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int reg_c = (ppc_cur_instruction >> 6) & 31; \
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double val_reg_a = GET_FPR(reg_a); \
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double val_reg_c = GET_FPR(reg_c);
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#define ppc_grab_regsfpdabc() \
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int reg_d = (ppc_cur_instruction >> 21) & 31; \
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int reg_a = (ppc_cur_instruction >> 16) & 31; \
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int reg_b = (ppc_cur_instruction >> 11) & 31; \
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int reg_c = (ppc_cur_instruction >> 6) & 31; \
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double val_reg_a = GET_FPR(reg_a); \
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double val_reg_b = GET_FPR(reg_b); \
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double val_reg_c = GET_FPR(reg_c);
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inline void ppc_update_cr1() {
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// copy FPSCR[FX|FEX|VX|OX] to CR1
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ppc_state.cr = (ppc_state.cr & ~CR_select::CR1_field) |
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((ppc_state.fpscr >> 4) & CR_select::CR1_field);
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}
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int64_t round_to_nearest(double f) {
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if (f >= 0.0) {
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return static_cast<int32_t>(static_cast<int64_t> (std::ceil(f)));
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} else {
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return static_cast<int32_t>(static_cast<int64_t> (std::floor(f)));
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}
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}
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void set_host_rounding_mode(uint8_t mode) {
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switch(mode & FPSCR::RN_MASK) {
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case 0:
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std::fesetround(FE_TONEAREST);
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break;
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case 1:
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std::fesetround(FE_TOWARDZERO);
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break;
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case 2:
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std::fesetround(FE_UPWARD);
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break;
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case 3:
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std::fesetround(FE_DOWNWARD);
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break;
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}
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}
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void update_fpscr(uint32_t new_fpscr) {
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if ((new_fpscr & FPSCR::RN_MASK) != (ppc_state.fpscr & FPSCR::RN_MASK))
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set_host_rounding_mode(new_fpscr & FPSCR::RN_MASK);
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ppc_state.fpscr = new_fpscr;
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}
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int64_t round_to_zero(double f) {
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return static_cast<int32_t>(std::trunc(f));
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}
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int64_t round_to_pos_inf(double f) {
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return static_cast<int32_t>(std::ceil(f));
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}
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int64_t round_to_neg_inf(double f) {
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return static_cast<int32_t>(std::floor(f));
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}
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void update_fex() {
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int fex_result = !!((ppc_state.fpscr & (ppc_state.fpscr << 22)) & 0x3E000000);
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ppc_state.fpscr = (ppc_state.fpscr & ~0x40000000) | (fex_result << 30);
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}
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template <typename T, const FPOP fpop>
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void ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, bool rc_flag = false) {
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T input_a = T(ppc_state.fpr[chosen_reg_1].dbl64_r);
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T input_b = T(ppc_state.fpr[chosen_reg_2].dbl64_r);
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ppc_state.fpscr &= 0x7fbfffff;
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switch (fpop) {
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case FPOP::DIV:
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if (std::isinf(input_a) && std::isinf(input_b)) {
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXIDI);
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} else if ((input_a == FP_ZERO) && (input_b == FP_ZERO)) {
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXZDZ);
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}
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update_fex();
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break;
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case FPOP::SUB:
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if (std::isinf(input_a) && std::isinf(input_b)) {
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXISI);
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}
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if (std::isnan(input_a) && std::isnan(input_b)) {
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXISI);
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}
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update_fex();
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break;
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case FPOP::ADD:
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if (std::isnan(input_a) && std::isnan(input_b)) {
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXISI);
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}
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update_fex();
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break;
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case FPOP::SQRT:
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if (std::isnan(input_b) || (input_b == -1.0)) {
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXSQRT);
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}
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update_fex();
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break;
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case FPOP::MUL:
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if (std::isnan(input_a) && std::isnan(input_b)) {
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ppc_state.fpscr |= (FPSCR::FX);
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}
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update_fex();
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break;
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}
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}
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static void fpresult_update(double set_result) {
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if (std::isnan(set_result)) {
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ppc_state.fpscr |= FPCC_FUNAN | FPRCD;
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} else {
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if (set_result > 0.0) {
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ppc_state.fpscr |= FPCC_POS;
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} else if (set_result < 0.0) {
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ppc_state.fpscr |= FPCC_NEG;
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} else {
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ppc_state.fpscr |= FPCC_ZERO;
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}
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if (std::isinf(set_result))
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ppc_state.fpscr |= FPCC_FUNAN;
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}
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}
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// Floating Point Arithmetic
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void dppc_interpreter::ppc_fadd() {
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ppc_grab_regsfpdab();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_b)) {
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ppc_state.fpscr |= FPCC_FUNAN;
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ppc_confirm_inf_nan<double, ADD>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = double(val_reg_a + val_reg_b);
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ppc_store_dfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fsub() {
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ppc_grab_regsfpdab();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_b)) {
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ppc_state.fpscr |= FPCC_FUNAN;
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ppc_confirm_inf_nan<double, SUB>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = double(val_reg_a - val_reg_b);
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ppc_store_dfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fdiv() {
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ppc_grab_regsfpdab();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_b)) {
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ppc_confirm_inf_nan<double, DIV>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = val_reg_a / val_reg_b;
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ppc_store_dfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fmul() {
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ppc_grab_regsfpdac();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
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ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
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}
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ppc_dblresult64_d = val_reg_a * val_reg_c;
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ppc_store_dfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fmadd() {
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ppc_grab_regsfpdabc();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
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ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
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}
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if (std::isnan(val_reg_b)) {
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ppc_confirm_inf_nan<double, ADD>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = std::fma(val_reg_a, val_reg_c, val_reg_b);
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ppc_store_dfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fmsub() {
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ppc_grab_regsfpdabc();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
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ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
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}
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if (std::isnan(val_reg_b)) {
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ppc_confirm_inf_nan<double, SUB>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = (val_reg_a * val_reg_c);
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ppc_dblresult64_d -= val_reg_b;
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ppc_store_dfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fnmadd() {
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ppc_grab_regsfpdabc();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
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ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
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}
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if (std::isnan(val_reg_b)) {
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ppc_confirm_inf_nan<double, ADD>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = std::fma(val_reg_a, val_reg_c, val_reg_b);
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ppc_dblresult64_d = -(ppc_dblresult64_d);
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ppc_store_dfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fnmsub() {
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ppc_grab_regsfpdabc();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
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ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
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}
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if (std::isnan(val_reg_b)) {
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ppc_confirm_inf_nan<double, SUB>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = (val_reg_a * val_reg_c);
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ppc_dblresult64_d -= val_reg_b;
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ppc_dblresult64_d = -(ppc_dblresult64_d);
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ppc_store_dfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fadds() {
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ppc_grab_regsfpdab();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_b)) {
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ppc_confirm_inf_nan<float, SUB>(reg_a, reg_b, rc_flag);
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}
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float ppc_fltresult32_d = val_reg_a + val_reg_b;
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ppc_dblresult64_d = (double)ppc_fltresult32_d;
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ppc_store_sfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fsubs() {
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ppc_grab_regsfpdab();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_b)) {
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ppc_confirm_inf_nan<float, SUB>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = (float)(val_reg_a - val_reg_b);
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ppc_store_sfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fdivs() {
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ppc_grab_regsfpdab();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_b)) {
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ppc_confirm_inf_nan<float, DIV>(reg_a, reg_b, rc_flag);
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}
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ppc_dblresult64_d = (float)(val_reg_a / val_reg_b);
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ppc_store_sfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fmuls() {
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ppc_grab_regsfpdac();
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if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
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ppc_confirm_inf_nan<float, MUL>(reg_a, reg_c, rc_flag);
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}
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ppc_dblresult64_d = (float)(val_reg_a * val_reg_c);
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ppc_store_sfpresult_flt(reg_d);
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fpresult_update(ppc_dblresult64_d);
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if (rc_flag)
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ppc_update_cr1();
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}
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void dppc_interpreter::ppc_fmadds() {
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ppc_grab_regsfpdabc();
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|
|
if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
|
|
ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
|
|
}
|
|
if (std::isnan(val_reg_b)) {
|
|
ppc_confirm_inf_nan<double, ADD>(reg_a, reg_b, rc_flag);
|
|
}
|
|
|
|
ppc_dblresult64_d = static_cast<double>(
|
|
std::fma((float)val_reg_a, (float)val_reg_c, (float)val_reg_b));
|
|
ppc_store_sfpresult_flt(reg_d);
|
|
fpresult_update(ppc_dblresult64_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fmsubs() {
|
|
ppc_grab_regsfpdabc();
|
|
|
|
if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
|
|
ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
|
|
}
|
|
if (std::isnan(val_reg_b)) {
|
|
ppc_confirm_inf_nan<double, ADD>(reg_a, reg_b, rc_flag);
|
|
}
|
|
|
|
float intermediate = float(val_reg_a * val_reg_c);
|
|
intermediate -= (float)val_reg_b;
|
|
ppc_dblresult64_d = static_cast<double>(intermediate);
|
|
ppc_store_sfpresult_flt(reg_d);
|
|
fpresult_update(ppc_dblresult64_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fnmadds() {
|
|
ppc_grab_regsfpdabc();
|
|
|
|
if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
|
|
ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
|
|
}
|
|
if (std::isnan(val_reg_b)) {
|
|
ppc_confirm_inf_nan<double, ADD>(reg_a, reg_b, rc_flag);
|
|
}
|
|
|
|
float intermediate = (float)val_reg_a * (float)val_reg_c;
|
|
intermediate += (float)val_reg_b;
|
|
intermediate = -intermediate;
|
|
ppc_dblresult64_d = static_cast<double>(intermediate);
|
|
ppc_store_sfpresult_flt(reg_d);
|
|
fpresult_update(ppc_dblresult64_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fnmsubs() {
|
|
ppc_grab_regsfpdabc();
|
|
|
|
|
|
if (std::isnan(val_reg_a) || std::isnan(val_reg_c)) {
|
|
ppc_confirm_inf_nan<double, MUL>(reg_a, reg_c, rc_flag);
|
|
}
|
|
if (std::isnan(val_reg_b)) {
|
|
ppc_confirm_inf_nan<double, SUB>(reg_a, reg_b, rc_flag);
|
|
}
|
|
|
|
float intermediate = (float)val_reg_a * (float)val_reg_c;
|
|
intermediate -= (float)val_reg_b;
|
|
intermediate = -intermediate;
|
|
ppc_dblresult64_d = static_cast<double>(intermediate);
|
|
ppc_store_sfpresult_flt(reg_d);
|
|
fpresult_update(ppc_dblresult64_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fabs() {
|
|
ppc_grab_regsfpdb();
|
|
|
|
ppc_dblresult64_d = abs(GET_FPR(reg_b));
|
|
|
|
ppc_store_dfpresult_flt(reg_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fnabs() {
|
|
ppc_grab_regsfpdb();
|
|
|
|
ppc_dblresult64_d = abs(GET_FPR(reg_b));
|
|
ppc_dblresult64_d = -ppc_dblresult64_d;
|
|
|
|
ppc_store_dfpresult_flt(reg_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fneg() {
|
|
ppc_grab_regsfpdb();
|
|
|
|
ppc_dblresult64_d = -(GET_FPR(reg_b));
|
|
|
|
ppc_store_dfpresult_flt(reg_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fsel() {
|
|
ppc_grab_regsfpdabc();
|
|
|
|
ppc_dblresult64_d = (val_reg_a >= -0.0) ? val_reg_c : val_reg_b;
|
|
|
|
ppc_store_dfpresult_flt(reg_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fsqrt() {
|
|
ppc_grab_regsfpdb();
|
|
double testd2 = (double)(GET_FPR(reg_b));
|
|
ppc_dblresult64_d = std::sqrt(testd2);
|
|
ppc_store_dfpresult_flt(reg_d);
|
|
ppc_confirm_inf_nan<double, SQRT>(0, reg_b, rc_flag);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fsqrts() {
|
|
ppc_grab_regsfpdb();
|
|
double testd2 = (double)(GET_FPR(reg_b));
|
|
ppc_dblresult64_d = (float)std::sqrt(testd2);
|
|
ppc_store_sfpresult_flt(reg_d);
|
|
ppc_confirm_inf_nan<float, SQRT>(0, reg_b, rc_flag);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_frsqrte() {
|
|
ppc_grab_regsfpdb();
|
|
double testd2 = (double)(GET_FPR(reg_b));
|
|
ppc_dblresult64_d = 1.0 / sqrt(testd2);
|
|
ppc_confirm_inf_nan<float, SQRT>(0, reg_b, rc_flag);
|
|
|
|
ppc_store_dfpresult_flt(reg_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_frsp() {
|
|
ppc_grab_regsfpdb();
|
|
ppc_dblresult64_d = (float)(GET_FPR(reg_b));
|
|
ppc_store_dfpresult_flt(reg_d);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fres() {
|
|
ppc_grab_regsfpdb();
|
|
double start_num = GET_FPR(reg_b);
|
|
float testf2 = (float)start_num;
|
|
testf2 = 1 / testf2;
|
|
ppc_dblresult64_d = (double)testf2;
|
|
ppc_store_dfpresult_flt(reg_d);
|
|
|
|
if (start_num == 0.0) {
|
|
ppc_state.fpscr |= FPSCR::ZX;
|
|
}
|
|
else if (std::isnan(start_num)) {
|
|
ppc_state.fpscr |= FPSCR::VXSNAN;
|
|
}
|
|
else if (std::isinf(start_num)){
|
|
ppc_state.fpscr &= 0xFFF9FFFF;
|
|
ppc_state.fpscr |= FPSCR::VXSNAN;
|
|
}
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
static void round_to_int(const uint8_t mode) {
|
|
ppc_grab_regsfpdb();
|
|
double val_reg_b = GET_FPR(reg_b);
|
|
|
|
if (std::isnan(val_reg_b)) {
|
|
ppc_state.fpscr &= ~(FPSCR::FR | FPSCR::FI);
|
|
ppc_state.fpscr |= (FPSCR::VXCVI | FPSCR::VX);
|
|
|
|
if (!(ppc_state.fpr[reg_b].int64_r & 0x0008000000000000)) // issnan
|
|
ppc_state.fpscr |= FPSCR::VXSNAN;
|
|
|
|
if (ppc_state.fpscr & FPSCR::VE) {
|
|
ppc_state.fpscr |= FPSCR::FEX; // VX=1 and VE=1 cause FEX to be set
|
|
ppc_floating_point_exception();
|
|
} else {
|
|
ppc_state.fpr[reg_d].int64_r = 0xFFF8000080000000ULL;
|
|
}
|
|
} else if (val_reg_b > static_cast<double>(0x7fffffff) ||
|
|
val_reg_b < -static_cast<double>(0x80000000)) {
|
|
ppc_state.fpscr &= ~(FPSCR::FR | FPSCR::FI);
|
|
ppc_state.fpscr |= (FPSCR::VXCVI | FPSCR::VX);
|
|
|
|
if (ppc_state.fpscr & FPSCR::VE) {
|
|
ppc_state.fpscr |= FPSCR::FEX; // VX=1 and VE=1 cause FEX to be set
|
|
ppc_floating_point_exception();
|
|
} else {
|
|
if (val_reg_b >= 0.0f)
|
|
ppc_state.fpr[reg_d].int64_r = 0xFFF800007FFFFFFFULL;
|
|
else
|
|
ppc_state.fpr[reg_d].int64_r = 0xFFF8000080000000ULL;
|
|
}
|
|
} else {
|
|
switch (mode & 0x3) {
|
|
case 0:
|
|
ppc_result64_d = round_to_nearest(val_reg_b);
|
|
break;
|
|
case 1:
|
|
ppc_result64_d = round_to_zero(val_reg_b);
|
|
break;
|
|
case 2:
|
|
ppc_result64_d = round_to_pos_inf(val_reg_b);
|
|
break;
|
|
case 3:
|
|
ppc_result64_d = round_to_neg_inf(val_reg_b);
|
|
break;
|
|
}
|
|
|
|
ppc_store_dfpresult_int(reg_d);
|
|
}
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fctiw() {
|
|
round_to_int(ppc_state.fpscr & 0x3);
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fctiwz() {
|
|
round_to_int(1);
|
|
}
|
|
|
|
// Floating Point Store and Load
|
|
|
|
void dppc_interpreter::ppc_lfs() {
|
|
ppc_grab_regsfpdia();
|
|
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
|
ppc_effective_address += (reg_a) ? val_reg_a : 0;
|
|
float result = (float)mmu_read_vmem<uint32_t>(ppc_effective_address);
|
|
ppc_state.fpr[reg_d].dbl64_r = (double)result;
|
|
}
|
|
|
|
|
|
void dppc_interpreter::ppc_lfsu() {
|
|
ppc_grab_regsfpdia();
|
|
if (reg_a) {
|
|
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
|
ppc_effective_address += (reg_a) ? val_reg_a : 0;
|
|
float result = (float)mmu_read_vmem<uint32_t>(ppc_effective_address);
|
|
ppc_state.fpr[reg_d].dbl64_r = (double)result;
|
|
ppc_state.gpr[reg_a] = ppc_effective_address;
|
|
} else {
|
|
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
|
}
|
|
}
|
|
|
|
void dppc_interpreter::ppc_lfsx() {
|
|
ppc_grab_regsfpdiab();
|
|
ppc_effective_address = (reg_a) ? val_reg_a + val_reg_b : val_reg_b;
|
|
float result = (float)mmu_read_vmem<uint32_t>(ppc_effective_address);
|
|
ppc_state.fpr[reg_d].dbl64_r = (double)result;
|
|
}
|
|
|
|
void dppc_interpreter::ppc_lfsux() {
|
|
ppc_grab_regsfpdiab();
|
|
if (reg_a) {
|
|
ppc_effective_address = val_reg_a + val_reg_b;
|
|
float result = (float)mmu_read_vmem<uint32_t>(ppc_effective_address);
|
|
ppc_state.fpr[reg_d].dbl64_r = (double)result;
|
|
ppc_state.gpr[reg_a] = ppc_effective_address;
|
|
} else {
|
|
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
|
}
|
|
}
|
|
|
|
void dppc_interpreter::ppc_lfd() {
|
|
ppc_grab_regsfpdia();
|
|
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
|
ppc_effective_address += (reg_a) ? val_reg_a : 0;
|
|
ppc_result64_d = mmu_read_vmem<uint64_t>(ppc_effective_address);
|
|
ppc_store_dfpresult_int(reg_d);
|
|
}
|
|
|
|
void dppc_interpreter::ppc_lfdu() {
|
|
ppc_grab_regsfpdia();
|
|
if (reg_a != 0) {
|
|
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
|
ppc_effective_address += val_reg_a;
|
|
ppc_result64_d = mmu_read_vmem<uint64_t>(ppc_effective_address);
|
|
ppc_store_dfpresult_int(reg_d);
|
|
ppc_state.gpr[reg_a] = ppc_effective_address;
|
|
} else {
|
|
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
|
}
|
|
}
|
|
|
|
void dppc_interpreter::ppc_lfdx() {
|
|
ppc_grab_regsfpdiab();
|
|
ppc_effective_address = (reg_a) ? val_reg_a + val_reg_b : val_reg_b;
|
|
ppc_result64_d = mmu_read_vmem<uint64_t>(ppc_effective_address);
|
|
ppc_store_dfpresult_int(reg_d);
|
|
}
|
|
|
|
void dppc_interpreter::ppc_lfdux() {
|
|
ppc_grab_regsfpdiab();
|
|
if (reg_a) {
|
|
ppc_effective_address = val_reg_a + val_reg_b;
|
|
ppc_result64_d = mmu_read_vmem<uint64_t>(ppc_effective_address);
|
|
ppc_store_dfpresult_int(reg_d);
|
|
ppc_state.gpr[reg_a] = ppc_effective_address;
|
|
} else {
|
|
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
|
}
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfs() {
|
|
ppc_grab_regsfpsia();
|
|
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
|
ppc_effective_address += (reg_a) ? val_reg_a : 0;
|
|
float result = ppc_state.fpr[reg_s].dbl64_r;
|
|
mmu_write_vmem<uint32_t>(ppc_effective_address, uint32_t(result));
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfsu() {
|
|
ppc_grab_regsfpsia();
|
|
if (reg_a != 0) {
|
|
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
|
ppc_effective_address += val_reg_a;
|
|
float result = ppc_state.fpr[reg_s].dbl64_r;
|
|
mmu_write_vmem<uint32_t>(ppc_effective_address, uint32_t(result));
|
|
ppc_state.gpr[reg_a] = ppc_effective_address;
|
|
} else {
|
|
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
|
}
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfsx() {
|
|
ppc_grab_regsfpsiab();
|
|
ppc_effective_address = (reg_a) ? val_reg_a + val_reg_b : val_reg_b;
|
|
float result = ppc_state.fpr[reg_s].dbl64_r;
|
|
mmu_write_vmem<uint32_t>(ppc_effective_address, uint32_t(result));
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfsux() {
|
|
ppc_grab_regsfpsiab();
|
|
if (reg_a) {
|
|
ppc_effective_address = val_reg_a + val_reg_b;
|
|
float result = ppc_state.fpr[reg_s].dbl64_r;
|
|
mmu_write_vmem<uint32_t>(ppc_effective_address, uint32_t(result));
|
|
ppc_state.gpr[reg_a] = ppc_effective_address;
|
|
} else {
|
|
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
|
}
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfd() {
|
|
ppc_grab_regsfpsia();
|
|
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
|
ppc_effective_address += (reg_a) ? val_reg_a : 0;
|
|
mmu_write_vmem<uint64_t>(ppc_effective_address, ppc_state.fpr[reg_s].int64_r);
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfdu() {
|
|
ppc_grab_regsfpsia();
|
|
if (reg_a != 0) {
|
|
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
|
ppc_effective_address += val_reg_a;
|
|
mmu_write_vmem<uint64_t>(ppc_effective_address, ppc_state.fpr[reg_s].int64_r);
|
|
ppc_state.gpr[reg_a] = ppc_effective_address;
|
|
} else {
|
|
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
|
}
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfdx() {
|
|
ppc_grab_regsfpsiab();
|
|
ppc_effective_address = (reg_a) ? val_reg_a + val_reg_b : val_reg_b;
|
|
mmu_write_vmem<uint64_t>(ppc_effective_address, ppc_state.fpr[reg_s].int64_r);
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfdux() {
|
|
ppc_grab_regsfpsiab();
|
|
if (reg_a != 0) {
|
|
ppc_effective_address = val_reg_a + val_reg_b;
|
|
mmu_write_vmem<uint64_t>(ppc_effective_address, ppc_state.fpr[reg_s].int64_r);
|
|
ppc_state.gpr[reg_a] = ppc_effective_address;
|
|
} else {
|
|
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
|
}
|
|
}
|
|
|
|
void dppc_interpreter::ppc_stfiwx() {
|
|
ppc_grab_regsfpsiab();
|
|
ppc_effective_address = (reg_a) ? val_reg_a + val_reg_b : val_reg_b;
|
|
mmu_write_vmem<uint32_t>(ppc_effective_address, (uint32_t)(ppc_state.fpr[reg_s].int64_r));
|
|
}
|
|
|
|
// Floating Point Register Transfer
|
|
|
|
void dppc_interpreter::ppc_fmr() {
|
|
ppc_grab_regsfpdb();
|
|
ppc_state.fpr[reg_d].dbl64_r = ppc_state.fpr[reg_b].dbl64_r;
|
|
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if (rc_flag)
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ppc_update_cr1();
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}
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|
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void dppc_interpreter::ppc_mffs() {
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ppc_grab_regsda();
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|
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ppc_state.fpr[reg_d].int64_r = (uint64_t)ppc_state.fpscr;
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|
|
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if (rc_flag)
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ppc_update_cr1();
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}
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|
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void dppc_interpreter::ppc_mtfsf() {
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int reg_b = (ppc_cur_instruction >> 11) & 0x1F;
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uint8_t fm = (ppc_cur_instruction >> 17) & 0xFF;
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|
|
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uint32_t cr_mask = 0;
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|
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if (fm == 0xFFU) // the fast case
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cr_mask = 0xFFFFFFFFUL;
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else { // the slow case
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if (fm & 0x80) cr_mask |= 0xF0000000UL;
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if (fm & 0x40) cr_mask |= 0x0F000000UL;
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if (fm & 0x20) cr_mask |= 0x00F00000UL;
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if (fm & 0x10) cr_mask |= 0x000F0000UL;
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if (fm & 0x08) cr_mask |= 0x0000F000UL;
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if (fm & 0x04) cr_mask |= 0x00000F00UL;
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if (fm & 0x02) cr_mask |= 0x000000F0UL;
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if (fm & 0x01) cr_mask |= 0x0000000FUL;
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}
|
|
|
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// ensure neither FEX nor VX will be changed
|
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cr_mask &= ~(FPSCR::FEX | FPSCR::VX);
|
|
|
|
// copy FPR[reg_b] to FPSCR under control of cr_mask
|
|
ppc_state.fpscr = (ppc_state.fpscr & ~cr_mask) | (ppc_state.fpr[reg_b].int64_r & cr_mask);
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_mtfsfi() {
|
|
int crf_d = (ppc_cur_instruction >> 21) & 0x1C;
|
|
uint32_t imm = (ppc_cur_instruction << 16) & 0xF0000000UL;
|
|
|
|
// prepare field mask and ensure that neither FEX nor VX will be changed
|
|
uint32_t mask = (0xF0000000UL >> crf_d) & ~(FPSCR::FEX | FPSCR::VX);
|
|
|
|
// copy imm to FPSCR[crf_d] under control of the field mask
|
|
ppc_state.fpscr = (ppc_state.fpscr & ~mask) | ((imm >> crf_d) & mask);
|
|
|
|
// TODO: update FEX and VX according to the "usual rule"
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_mtfsb0() {
|
|
int crf_d = (ppc_cur_instruction >> 21) & 0x1F;
|
|
if (!crf_d || (crf_d > 2)) { // FEX and VX can't be explicitely cleared
|
|
ppc_state.fpscr &= ~(0x80000000UL >> crf_d);
|
|
}
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_mtfsb1() {
|
|
int crf_d = (ppc_cur_instruction >> 21) & 0x1F;
|
|
if (!crf_d || (crf_d > 2)) { // FEX and VX can't be explicitely set
|
|
ppc_state.fpscr |= (0x80000000UL >> crf_d);
|
|
}
|
|
|
|
if (rc_flag)
|
|
ppc_update_cr1();
|
|
}
|
|
|
|
void dppc_interpreter::ppc_mcrfs() {
|
|
int crf_d = (ppc_cur_instruction >> 21) & 0x1C;
|
|
int crf_s = (ppc_cur_instruction >> 16) & 0x1C;
|
|
ppc_state.cr = (
|
|
(ppc_state.cr & ~(0xF0000000UL >> crf_d)) |
|
|
(((ppc_state.fpscr << crf_s) & 0xF0000000UL) >> crf_d)
|
|
);
|
|
ppc_state.fpscr &= ~((0xF0000000UL >> crf_s) & (
|
|
// keep only the FPSCR bits that can be explicitly cleared
|
|
FPSCR::FX | FPSCR::OX |
|
|
FPSCR::UX | FPSCR::ZX | FPSCR::XX | FPSCR::VXSNAN |
|
|
FPSCR::VXISI | FPSCR::VXIDI | FPSCR::VXZDZ | FPSCR::VXIMZ |
|
|
FPSCR::VXVC |
|
|
FPSCR::VXSOFT | FPSCR::VXSQRT | FPSCR::VXCVI
|
|
));
|
|
}
|
|
|
|
// Floating Point Comparisons
|
|
|
|
void dppc_interpreter::ppc_fcmpo() {
|
|
ppc_grab_regsfpsab();
|
|
|
|
uint32_t cmp_c = 0;
|
|
|
|
if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
|
|
// TODO: test for SNAN operands
|
|
// for now, assume that at least one of the operands is QNAN
|
|
ppc_state.fpscr |= FPSCR::VXVC;
|
|
cmp_c |= CRx_bit::CR_SO;
|
|
}
|
|
else if (db_test_a < db_test_b) {
|
|
cmp_c |= CRx_bit::CR_LT;
|
|
}
|
|
else if (db_test_a > db_test_b) {
|
|
cmp_c |= CRx_bit::CR_GT;
|
|
}
|
|
else {
|
|
cmp_c |= CRx_bit::CR_EQ;
|
|
}
|
|
|
|
ppc_state.fpscr = (ppc_state.fpscr & ~FPSCR::FPCC_MASK) | (cmp_c >> 16); // update FPCC
|
|
ppc_state.cr = ((ppc_state.cr & ~(0xF0000000 >> crf_d)) | ((cmp_c) >> crf_d));
|
|
}
|
|
|
|
void dppc_interpreter::ppc_fcmpu() {
|
|
ppc_grab_regsfpsab();
|
|
|
|
uint32_t cmp_c = 0;
|
|
|
|
if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
|
|
// TODO: test for SNAN operands
|
|
cmp_c |= CRx_bit::CR_SO;
|
|
}
|
|
else if (db_test_a < db_test_b) {
|
|
cmp_c |= CRx_bit::CR_LT;
|
|
}
|
|
else if (db_test_a > db_test_b) {
|
|
cmp_c |= CRx_bit::CR_GT;
|
|
}
|
|
else {
|
|
cmp_c |= CRx_bit::CR_EQ;
|
|
}
|
|
|
|
ppc_state.fpscr = (ppc_state.fpscr & ~FPSCR::FPCC_MASK) | (cmp_c >> 16); // update FPCC
|
|
ppc_state.cr = ((ppc_state.cr & ~(0xF0000000 >> crf_d)) | ((cmp_c) >> crf_d));
|
|
}
|