mirror of
https://github.com/dingusdev/dingusppc.git
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158 lines
3.6 KiB
C++
158 lines
3.6 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file MESH (Macintosh Enhanced SCSI Hardware) controller definitions. */
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#ifndef MESH_H
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#define MESH_H
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#include <devices/common/hwcomponent.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/scsi/scsi.h>
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#include <cinttypes>
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#include <memory>
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// Chip ID returned by the MESH cell inside the Heathrow ASIC
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#define HeathrowMESHID 4
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namespace MeshScsi {
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// MESH registers offsets.
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enum MeshReg : uint8_t {
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XferCount0 = 0,
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XferCount1 = 1,
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FIFO = 2,
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Sequence = 3,
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BusStatus0 = 4,
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BusStatus1 = 5,
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FIFOCount = 6,
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Exception = 7,
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Error = 8,
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IntMask = 9,
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Interrupt = 0xA,
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SourceID = 0xB,
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DestID = 0xC,
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SyncParms = 0xD,
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MeshID = 0xE,
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SelTimeOut = 0xF
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};
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// MESH Sequencer commands.
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enum SeqCmd : uint8_t {
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NoOperation = 0,
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Arbitrate = 1,
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Select = 2,
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DisReselect = 0xD,
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ResetMesh = 0xE,
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FlushFIFO = 0xF,
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};
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// Exception register bits.
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enum {
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EXC_SEL_TIMEOUT = 1 << 0,
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EXC_PHASE_MM = 1 << 1,
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EXC_ARB_LOST = 1 << 2,
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};
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// Interrupt register bits.
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enum {
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INT_CMD_DONE = 1 << 0,
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INT_EXCEPTION = 1 << 1,
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INT_ERROR = 1 << 2,
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INT_MASK = INT_CMD_DONE | INT_EXCEPTION | INT_ERROR
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};
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enum SeqState : uint32_t {
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IDLE = 0,
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BUS_FREE,
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ARB_BEGIN,
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ARB_END,
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SEL_BEGIN,
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SEL_END,
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SEND_MSG,
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SEND_CMD,
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CMD_COMPLETE,
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XFER_BEGIN,
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XFER_END,
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SEND_DATA,
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RCV_DATA,
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RCV_STATUS,
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RCV_MESSAGE,
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};
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}; // namespace MeshScsi
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class MeshController : public HWComponent {
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public:
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MeshController(uint8_t mesh_id) {
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supports_types(HWCompType::SCSI_HOST | HWCompType::SCSI_DEV);
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this->chip_id = mesh_id;
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this->reset(true);
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};
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~MeshController() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<MeshController>(new MeshController(HeathrowMESHID));
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}
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// MESH registers access
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uint8_t read(uint8_t reg_offset);
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void write(uint8_t reg_offset, uint8_t value);
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// HWComponent methods
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int device_postinit();
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protected:
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void reset(bool is_hard_reset);
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void perform_command(const uint8_t cmd);
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void seq_defer_state(uint64_t delay_ns);
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void sequencer();
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void update_irq();
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private:
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uint8_t chip_id;
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uint8_t int_mask;
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uint8_t int_stat = 0;
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uint8_t sync_params;
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uint8_t src_id;
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uint8_t dst_id;
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uint8_t cur_cmd;
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uint8_t error;
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uint8_t exception;
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ScsiBus* bus_obj;
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uint16_t bus_stat;
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// Sequencer state
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uint32_t seq_timer_id;
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uint32_t cur_state;
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uint32_t next_state;
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// interrupt related stuff
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InterruptCtrl* int_ctrl = nullptr;
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uint32_t irq_id = 0;
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uint8_t irq = 0;
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};
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#endif // MESH_H
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