313 lines
11 KiB
C++
313 lines
11 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MPC106 (Grackle) emulation. */
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#include <devices/common/hwcomponent.h>
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#include <devices/common/mmiodevice.h>
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#include <devices/deviceregistry.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <devices/memctrl/mpc106.h>
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#include <loguru.hpp>
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#include <memaccess.h>
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#include <cinttypes>
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#include <cstring>
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#include <string>
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#include <vector>
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MPC106::MPC106() : MemCtrlBase(), PCIDevice("Grackle"), PCIHost()
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{
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supports_types(HWCompType::MEM_CTRL | HWCompType::MMIO_DEV |
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HWCompType::PCI_HOST | HWCompType::PCI_DEV);
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// populate PCI config header
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this->vendor_id = PCI_VENDOR_MOTOROLA;
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this->device_id = 0x0002;
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this->class_rev = 0x06000040;
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this->cache_ln_sz = 8;
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this->command = 6;
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this->status = 0x80;
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// assign PCI device number zero to myself
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this->pci_register_device(DEV_FUN(0,0), this);
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// add PCI/ISA I/O space, 64K for now
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add_mmio_region(0xFE000000, 0x10000, this);
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// add memory mapped I/O region for MPC106 registers
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add_mmio_region(0xFEC00000, 0x300000, this);
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}
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int MPC106::device_postinit()
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{
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std::string pci_dev_name;
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static const std::map<std::string, int> pci_slots = {
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{"pci_A1", DEV_FUN(0xD,0)}, {"pci_B1", DEV_FUN(0xE,0)}, {"pci_C1", DEV_FUN(0xF,0)}
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};
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for (auto& slot : pci_slots) {
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pci_dev_name = GET_STR_PROP(slot.first);
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if (!pci_dev_name.empty()) {
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this->attach_pci_device(pci_dev_name, slot.second);
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}
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}
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return 0;
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}
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uint32_t MPC106::read(uint32_t rgn_start, uint32_t offset, int size) {
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uint32_t result;
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if (rgn_start == 0xFE000000) {
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// broadcast I/O request to devices that support I/O space
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// until a device returns true that means "request accepted"
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for (auto& dev : this->io_space_devs) {
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if (dev->pci_io_read(offset, size, &result)) {
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return result;
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}
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}
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LOG_F(ERROR, "Attempt to read from unmapped PCI I/O space, offset=0x%X", offset);
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// FIXME: add machine check exception (DEFAULT CATCH!, code=FFF00200)
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} else {
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if (offset >= 0x200000) {
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
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return pci_read(offset, size);
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} else {
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return this->config_addr;
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}
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}
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return 0;
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}
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void MPC106::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {
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if (rgn_start == 0xFE000000) {
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// broadcast I/O request to devices that support I/O space
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// until a device returns true that means "request accepted"
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for (auto& dev : this->io_space_devs) {
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if (dev->pci_io_write(offset, value, size)) {
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return;
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}
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}
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LOG_F(ERROR, "Attempt to write to unmapped PCI I/O space, offset=0x%X", offset);
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} else {
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if (offset < 0x200000) {
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this->config_addr = value;
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} else {
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
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return pci_write(offset, value, size);
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}
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}
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}
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uint32_t MPC106::pci_read(uint32_t offset, uint32_t size) {
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int bus_num = (this->config_addr >> 8) & 0xFF;
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int dev_num = (this->config_addr >> 19) & 0x1F;
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int fun_num = (this->config_addr >> 16) & 0x07;
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int reg_offs = (this->config_addr >> 24) & 0xFC;
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if (bus_num) {
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LOG_F(ERROR, "%s: read attempt from non-local PCI bus, %02x:%02x.%x @%02x",
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + (offset & 3));
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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if (this->dev_map.count(DEV_FUN(dev_num,fun_num))) {
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AccessDetails details;
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details.offset = offset & 3;
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details.size = size;
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details.flags = PCI_CONFIG_TYPE_0 | PCI_CONFIG_READ;
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uint32_t result = this->dev_map[DEV_FUN(dev_num,fun_num)]->pci_cfg_read(reg_offs, details);
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return pci_conv_rd_data(result, details);
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} else {
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LOG_F(ERROR, "%s: read attempt from non-existing PCI device ??:%02x.%x @%02x",
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this->name.c_str(), dev_num, fun_num, reg_offs + (offset & 3));
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}
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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void MPC106::pci_write(uint32_t offset, uint32_t value, uint32_t size) {
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int bus_num = (this->config_addr >> 8) & 0xFF;
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int dev_num = (this->config_addr >> 19) & 0x1F;
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int fun_num = (this->config_addr >> 16) & 0x07;
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int reg_offs = (this->config_addr >> 24) & 0xFC;
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if (bus_num) {
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LOG_F(ERROR, "%s: write attempt to non-local PCI bus, %02x:%02x.%x @%02x",
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + (offset & 3));
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return;
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}
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if (this->dev_map.count(DEV_FUN(dev_num,fun_num))) {
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AccessDetails details;
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details.offset = offset & 3;
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details.size = size;
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details.flags = PCI_CONFIG_TYPE_0 | PCI_CONFIG_WRITE;
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if (size == 4 && !details.offset) { // aligned DWORD writes -> fast path
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this->dev_map[DEV_FUN(dev_num,fun_num)]->pci_cfg_write(reg_offs, BYTESWAP_32(value), details);
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} else { // otherwise perform necessary data transformations -> slow path
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uint32_t old_val = this->dev_map[DEV_FUN(dev_num,fun_num)]->pci_cfg_read(reg_offs, details);
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uint32_t new_val = pci_conv_wr_data(old_val, value, details);
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this->dev_map[DEV_FUN(dev_num,fun_num)]->pci_cfg_write(reg_offs, new_val, details);
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}
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} else {
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LOG_F(ERROR, "%s: write attempt to non-existing PCI device ??:%02x.%x @%02x",
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this->name.c_str(), dev_num, fun_num, reg_offs + (offset & 3));
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}
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}
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uint32_t MPC106::pci_cfg_read(uint32_t reg_offs, AccessDetails &details) {
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if (reg_offs < 64) {
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return PCIDevice::pci_cfg_read(reg_offs, details);
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}
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switch (reg_offs) {
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case GrackleReg::CFG10:
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return 0;
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case GrackleReg::PMCR1:
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return (this->odcr << 24) | (this->pmcr2 << 16) | this->pmcr1;
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case GrackleReg::MBER:
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return this->mem_bank_en;
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case GrackleReg::PICR1:
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return this->picr1;
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case GrackleReg::PICR2:
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return this->picr2;
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case GrackleReg::MCCR1:
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return this->mccr1;
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default:
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LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER();
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}
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return 0; // PCI Spec §6.1
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}
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void MPC106::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details) {
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if (reg_offs < 64) {
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PCIDevice::pci_cfg_write(reg_offs, value, details);
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return;
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}
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switch (reg_offs) {
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case GrackleReg::CFG10:
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// Open Firmware writes 0 to subordinate bus # - we don't care
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break;
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case GrackleReg::PMCR1:
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this->pmcr1 = value & 0xFFFFU;
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this->pmcr2 = (value >> 16) & 0xFF;
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this->odcr = value >> 24;
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break;
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case GrackleReg::MSAR1:
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case GrackleReg::MSAR2:
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this->mem_start[(reg_offs >> 2) & 1] = value;
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break;
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case GrackleReg::EMSAR1:
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case GrackleReg::EMSAR2:
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this->ext_mem_start[(reg_offs >> 2) & 1] = value;
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break;
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case GrackleReg::MEAR1:
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case GrackleReg::MEAR2:
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this->mem_end[(reg_offs >> 2) & 1] = value;
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break;
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case GrackleReg::EMEAR1:
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case GrackleReg::EMEAR2:
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this->ext_mem_end[(reg_offs >> 2) & 1] = value;
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break;
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case GrackleReg::MBER:
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this->mem_bank_en = value & 0xFFU;
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break;
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case GrackleReg::PICR1:
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this->picr1 = value;
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break;
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case GrackleReg::PICR2:
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this->picr2 = value;
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break;
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case GrackleReg::MCCR1:
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if ((value ^ this->mccr1) & MEMGO) {
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if (value & MEMGO)
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setup_ram();
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}
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this->mccr1 = value;
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break;
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case GrackleReg::MCCR2:
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this->mccr2 = value;
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break;
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case GrackleReg::MCCR3:
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this->mccr3 = value;
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break;
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case GrackleReg::MCCR4:
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this->mccr4 = value;
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break;
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default:
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LOG_WRITE_UNIMPLEMENTED_CONFIG_REGISTER();
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}
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}
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void MPC106::setup_ram() {
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uint32_t mem_start, mem_end, ext_mem_start, ext_mem_end, bank_start, bank_end;
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uint32_t ram_size = 0;
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for (int bank = 0; bank < 8; bank++) {
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if (this->mem_bank_en & (1 << bank)) {
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if (bank < 4) {
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mem_start = this->mem_start[0];
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ext_mem_start = this->ext_mem_start[0];
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mem_end = this->mem_end[0];
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ext_mem_end = this->ext_mem_end[0];
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} else {
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mem_start = this->mem_start[1];
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ext_mem_start = this->ext_mem_start[1];
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mem_end = this->mem_end[1];
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ext_mem_end = this->ext_mem_end[1];
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}
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bank_start = (((ext_mem_start >> bank * 8) & 3) << 30) |
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(((mem_start >> bank * 8) & 0xFF) << 20);
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bank_end = (((ext_mem_end >> bank * 8) & 3) << 30) |
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(((mem_end >> bank * 8) & 0xFF) << 20) | 0xFFFFFUL;
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if (bank && bank_start != ram_size)
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LOG_F(WARNING, "Grackle: RAM not contiguous!");
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ram_size += bank_end - bank_start + 1;
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}
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}
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if (!this->add_ram_region(0, ram_size)) {
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LOG_F(WARNING, "Grackle: RAM allocation 0x%X..0x%X failed (maybe already exists?)",
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0, ram_size - 1);
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}
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}
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static const PropMap Grackle_Properties = {
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{"pci_A1",
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new StrProperty("")},
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{"pci_B1",
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new StrProperty("")},
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{"pci_C1",
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new StrProperty("")},
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};
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static const DeviceDescription Grackle_Descriptor = {
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MPC106::create, {}, Grackle_Properties
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};
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REGISTER_DEVICE(Grackle, Grackle_Descriptor);
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