mirror of
https://github.com/dingusdev/dingusppc.git
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123 lines
3.3 KiB
C++
123 lines
3.3 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file SCSI bus controller definitions. */
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#ifndef SCSI_BUS_CTRL_H
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#define SCSI_BUS_CTRL_H
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#include <devices/common/dmacore.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/scsi/scsi.h>
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#include <cinttypes>
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#include <string>
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namespace Scsi_Bus_Controller {
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/** SCSI sequencer states. */
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enum SeqState : uint32_t {
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IDLE = 0,
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BUS_FREE,
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ARB_BEGIN,
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ARB_END,
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SEL_BEGIN,
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SEL_END,
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SEND_MSG,
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SEND_CMD,
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CMD_COMPLETE,
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XFER_BEGIN,
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XFER_END,
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SEND_DATA,
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RCV_DATA,
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RCV_STATUS,
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RCV_MESSAGE,
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};
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};
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/** Sequencer error codes. */
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enum : int {
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ARB_LOST = 1,
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SEL_TIMEOUT,
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};
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#define DATA_FIFO_DEPTH 16
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class ScsiBusController : public ScsiDevice, public DmaDevice {
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public:
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ScsiBusController(std::string name, uint8_t my_bus_id=7) : ScsiDevice(name, my_bus_id) {
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supports_types(HWCompType::SCSI_HOST | HWCompType::SCSI_DEV);
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}
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~ScsiBusController() = default;
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// implements SCSI FSM
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void sequencer();
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virtual void step_completed() = 0;
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virtual void report_error(const int error) = 0;
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// ScsiDevice methods
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void notify(ScsiMsg msg_type, int param);
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bool prepare_data() { return false; };
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bool get_more_data() { return false; };
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bool has_data() { return false; };
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bool rcv_data();
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int send_data(uint8_t* dst_ptr, int count);
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void process_command() {};
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// DmaDevice methods
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int xfer_from(uint8_t *buf, int len); // must be marked OVERRIDE!
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protected:
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void seq_defer_state(uint64_t delay_ns);
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void update_irq();
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void fifo_push(const uint8_t data);
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uint8_t fifo_pop();
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ScsiBus* bus_obj = nullptr;
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uint8_t src_id;
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uint8_t dst_id;
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bool is_dma_cmd = false;
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bool is_initiator = true;
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bool assert_atn = false;
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// Data FIFO state
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int fifo_pos = 0;
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int to_xfer = 0;
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uint32_t xfer_count = 0;
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int bytes_out = 0;
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uint8_t data_fifo[DATA_FIFO_DEPTH] = {};
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// Sequencer state
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uint32_t seq_timer_id = 0;
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uint32_t cur_state = Scsi_Bus_Controller::SeqState::IDLE;
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uint32_t next_state = Scsi_Bus_Controller::SeqState::IDLE;
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int cur_bus_phase = 0;
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// interrupt related stuff
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InterruptCtrl* int_ctrl = nullptr;
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uint32_t irq_id = 0;
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uint8_t irq = 0;
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uint8_t int_mask = 0;
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uint8_t int_stat = 0;
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};
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#endif // SCSI_BUS_CTRL_H
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