mirror of
https://github.com/dingusdev/dingusppc.git
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111 lines
3.4 KiB
C++
111 lines
3.4 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-20 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <atirage.h>
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#include <cstdint>
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#include "endianswap.h"
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#include "memreadwrite.h"
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#include "pcidevice.h"
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#include <thirdparty/loguru/loguru.hpp>
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ATIRage::ATIRage(uint16_t dev_id) : PCIDevice("ati-rage")
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{
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WRITE_DWORD_BE_A(&this->pci_cfg[0], (dev_id << 16) | ATI_PCI_VENDOR_ID);
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WRITE_DWORD_BE_A(&this->pci_cfg[8], 0x0300005C);
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WRITE_DWORD_BE_A(&this->pci_cfg[0x3C], 0x00080100);
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}
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uint32_t ATIRage::pci_cfg_read(uint32_t reg_offs, uint32_t size)
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{
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uint32_t res = 0;
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LOG_F(INFO, "Reading ATI Rage config space, offset = 0x%X, size=%d", reg_offs, size);
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switch (size) {
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case 4:
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res = READ_DWORD_LE_U(&this->pci_cfg[reg_offs]);
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break;
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case 2:
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res = READ_WORD_LE_U(&this->pci_cfg[reg_offs]);
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break;
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case 1:
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res = this->pci_cfg[reg_offs];
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break;
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default:
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LOG_F(WARNING, "ATI Rage pci_cfg_read(): invalid size %d", size);
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}
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LOG_F(INFO, "Return value: 0x%X", res);
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return res;
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}
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void ATIRage::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size)
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{
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LOG_F(INFO, "Writing into ATI Rage PCI config space, offset = 0x%X, val=0x%X size=%d",
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reg_offs, BYTESWAP_32(value), size);
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switch (reg_offs) {
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case 0x10: /* BAR 0 */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_LE_A(&this->pci_cfg[0x10], 0xFF000008);
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}
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else {
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WRITE_DWORD_LE_A(&this->pci_cfg[0x10], value);
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}
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break;
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case 0x14: /* BAR 1: I/O space base, 256 bytes wide */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_LE_A(&this->pci_cfg[0x14], 0x0000FFF1);
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}
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else {
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WRITE_DWORD_LE_A(&this->pci_cfg[0x14], value);
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}
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case 0x18: /* BAR 2 */
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if (value == 0xFFFFFFFFUL) {
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WRITE_DWORD_LE_A(&this->pci_cfg[0x18], 0xFFFFF000);
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}
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else {
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WRITE_DWORD_LE_A(&this->pci_cfg[0x18], value);
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}
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break;
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case 0x1C: /* BAR 3: unimplemented */
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case 0x20: /* BAR 4: unimplemented */
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case 0x24: /* BAR 5: unimplemented */
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case 0x30: /* Expansion ROM Base Addr: unimplemented */
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WRITE_DWORD_LE_A(&this->pci_cfg[reg_offs], 0);
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break;
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default:
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WRITE_DWORD_LE_A(&this->pci_cfg[reg_offs], value);
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}
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}
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uint32_t ATIRage::read(uint32_t reg_start, uint32_t offset, int size)
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{
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LOG_F(INFO, "Reading reg=%X, size %d", offset, size);
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return 0;
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}
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void ATIRage::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
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{
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LOG_F(INFO, "Writing reg=%X, value=%X, size %d", offset, value, size);
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}
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