mirror of
https://github.com/dingusdev/dingusppc.git
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312 lines
10 KiB
C++
312 lines
10 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file MESH (Macintosh Enhanced SCSI Hardware) controller emulation. */
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#include <core/timermanager.h>
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#include <devices/common/hwcomponent.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/scsi/mesh.h>
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#include <devices/common/scsi/scsi.h>
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#include <devices/deviceregistry.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <cinttypes>
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using namespace MeshScsi;
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int MeshController::device_postinit() {
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this->bus_obj = dynamic_cast<ScsiBus*>(gMachineObj->get_comp_by_name("ScsiMesh"));
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if (bus_obj) {
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bus_obj->register_device(7, static_cast<ScsiDevice*>(this));
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bus_obj->attach_scsi_devices("2");
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}
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this->int_ctrl = dynamic_cast<InterruptCtrl*>(
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gMachineObj->get_comp_by_type(HWCompType::INT_CTRL));
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this->irq_id = this->int_ctrl->register_dev_int(IntSrc::SCSI_MESH);
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return 0;
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}
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void MeshController::reset(bool is_hard_reset) {
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this->cur_cmd = SeqCmd::NoOperation;
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this->fifo_pos = 0;
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this->int_mask = 0;
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this->exception = 0;
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this->xfer_count = 0;
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this->src_id = 7;
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if (is_hard_reset) {
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this->bus_stat = 0;
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this->sync_params = (0 << 16) | 2; // fast async operation (guessed)
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}
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}
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uint8_t MeshController::read(uint8_t reg_offset) {
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switch(reg_offset) {
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case MeshReg::XferCount0:
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return this->xfer_count & 0xFFU;
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case MeshReg::XferCount1:
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return (this->xfer_count >> 8) & 0xFFU;
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case MeshReg::FIFO:
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return this->fifo_pop();
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case MeshReg::Sequence:
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return this->cur_cmd;
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case MeshReg::BusStatus0:
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return this->bus_obj->test_ctrl_lines(0xFFU);
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case MeshReg::BusStatus1:
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return this->bus_obj->test_ctrl_lines(0xE000U) >> 8;
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case MeshReg::FIFOCount:
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return this->fifo_pos;
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case MeshReg::Exception:
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return this->exception;
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case MeshReg::Error:
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return 0;
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case MeshReg::IntMask:
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return this->int_mask;
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case MeshReg::Interrupt:
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return this->int_stat;
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case MeshReg::DestID:
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return this->dst_id;
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case MeshReg::SyncParms:
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return this->sync_params;
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case MeshReg::MeshID:
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return this->chip_id; // tell them who we are
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default:
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LOG_F(WARNING, "MESH: read from unimplemented register at offset 0x%x", reg_offset);
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}
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return 0;
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}
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void MeshController::write(uint8_t reg_offset, uint8_t value) {
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uint16_t new_stat;
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switch(reg_offset) {
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case MeshReg::XferCount0:
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this->xfer_count = (this->xfer_count & ~0xFFU) | value;
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break;
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case MeshReg::XferCount1:
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this->xfer_count = (this->xfer_count & ~0xFF00U) | (value << 8);
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break;
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case MeshReg::FIFO:
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this->fifo_push(value);
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break;
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case MeshReg::Sequence:
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perform_command(value);
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break;
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case MeshReg::BusStatus0:
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this->update_bus_status((this->bus_stat & 0xFF00U) | value);
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break;
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case MeshReg::BusStatus1:
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this->update_bus_status((this->bus_stat & 0xFFU) | (value << 8));
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break;
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case MeshReg::IntMask:
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this->int_mask = value;
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break;
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case MeshReg::Interrupt:
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this->int_stat &= ~(value & INT_MASK); // clear requested interrupt bits
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update_irq();
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break;
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case MeshReg::SourceID:
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this->src_id = value;
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break;
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case MeshReg::DestID:
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this->dst_id = value;
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break;
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case MeshReg::SyncParms:
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this->sync_params = value;
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break;
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case MeshReg::SelTimeOut:
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LOG_F(9, "MESH: selection timeout set to 0x%x", value);
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break;
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default:
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LOG_F(WARNING, "MESH: write to unimplemented register at offset 0x%x",
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reg_offset);
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}
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}
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void MeshController::perform_command(const uint8_t cmd) {
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this->cur_cmd = cmd;
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this->int_stat &= ~INT_CMD_DONE;
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this->is_dma_cmd = !!(this->cur_cmd & 0x80);
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switch (this->cur_cmd & 0xF) {
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case SeqCmd::Arbitrate:
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this->exception &= EXC_ARB_LOST;
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this->bus_obj->release_ctrl_lines(this->src_id);
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this->cur_state = Scsi_Bus_Controller::SeqState::BUS_FREE;
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this->sequencer();
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break;
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case SeqCmd::Select:
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this->assert_atn = !!(this->cur_cmd & 0x20);
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this->exception &= EXC_SEL_TIMEOUT;
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this->cur_state = Scsi_Bus_Controller::SeqState::SEL_BEGIN;
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this->sequencer();
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break;
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case SeqCmd::Command:
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if (this->bus_obj->current_phase() != ScsiPhase::COMMAND)
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LOG_F(WARNING, "%s: not in COMMAND phase", this->name.c_str());
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this->cur_state = Scsi_Bus_Controller::SeqState::SEND_CMD;
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if (this->fifo_pos)
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this->sequencer();
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break;
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case SeqCmd::Status:
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if (this->bus_obj->current_phase() != ScsiPhase::STATUS)
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LOG_F(WARNING, "%s: not in STATUS phase", this->name.c_str());
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this->to_xfer = this->xfer_count;
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this->cur_state = Scsi_Bus_Controller::SeqState::RCV_STATUS;
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this->sequencer();
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break;
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case SeqCmd::DataOut:
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if (this->bus_obj->current_phase() != ScsiPhase::DATA_OUT)
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LOG_F(WARNING, "%s: not in DATA OUT phase", this->name.c_str());
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this->to_xfer = this->xfer_count ? this->xfer_count : 65536;
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this->cur_state = Scsi_Bus_Controller::SeqState::XFER_BEGIN;
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this->sequencer();
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break;
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case SeqCmd::DataIn:
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if (this->bus_obj->current_phase() != ScsiPhase::DATA_IN)
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LOG_F(WARNING, "%s: not in DATA IN phase", this->name.c_str());
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this->to_xfer = this->xfer_count ? this->xfer_count : 65536;
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this->cur_state = Scsi_Bus_Controller::SeqState::XFER_BEGIN;
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this->sequencer();
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break;
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case SeqCmd::MessageOut:
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if (this->bus_obj->current_phase() != ScsiPhase::MESSAGE_OUT)
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LOG_F(WARNING, "%s: not in MESSAGE OUT phase", this->name.c_str());
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this->to_xfer = this->xfer_count;
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this->cur_state = Scsi_Bus_Controller::SeqState::SEND_MSG;
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this->sequencer();
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break;
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case SeqCmd::MessageIn:
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if (this->bus_obj->current_phase() != ScsiPhase::MESSAGE_IN)
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LOG_F(WARNING, "%s: not in MESSAGE IN phase", this->name.c_str());
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this->to_xfer = this->xfer_count;
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this->cur_state = Scsi_Bus_Controller::SeqState::RCV_MESSAGE;
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this->sequencer();
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break;
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case SeqCmd::BusFree:
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this->bus_obj->release_ctrl_line(this->src_id, SCSI_CTRL_ACK);
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// generate phase mismatch exception
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// if the target is still connected
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if (this->bus_obj->test_ctrl_lines(SCSI_CTRL_BSY)) {
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this->exception |= EXC_PHASE_MM;
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this->int_stat |= INT_EXCEPTION;
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} else // say ok because we got the expected bus free phase
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this->int_stat |= INT_CMD_DONE;
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this->update_irq();
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break;
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case SeqCmd::EnaParityCheck:
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this->check_parity = true;
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break;
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case SeqCmd::DisParityCheck:
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this->check_parity = false;
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break;
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case SeqCmd::EnaReselect:
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LOG_F(9, "MESH: EnaReselect stub invoked");
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this->int_stat |= INT_CMD_DONE;
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break;
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case SeqCmd::DisReselect:
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LOG_F(9, "MESH: DisReselect stub invoked");
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this->int_stat |= INT_CMD_DONE;
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break;
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case SeqCmd::ResetMesh:
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this->reset(false);
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this->int_stat |= INT_CMD_DONE;
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update_irq();
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break;
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case SeqCmd::FlushFIFO:
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this->fifo_pos = 0;
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break;
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default:
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LOG_F(ERROR, "MESH: unsupported sequencer command 0x%X", this->cur_cmd);
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}
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}
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void MeshController::update_bus_status(const uint16_t new_stat) {
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uint16_t mask;
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// update the lower part (BusStatus0)
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if ((new_stat ^ this->bus_stat) & 0xFF) {
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for (mask = SCSI_CTRL_REQ; mask >= SCSI_CTRL_IO; mask >>= 1) {
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if ((new_stat ^ this->bus_stat) & mask) {
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if (new_stat & mask)
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this->bus_obj->assert_ctrl_line(this->src_id, mask);
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else
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this->bus_obj->release_ctrl_line(this->src_id, mask);
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}
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}
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}
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// update the upper part (BusStatus1)
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if ((new_stat ^ this->bus_stat) & 0xFF00U) {
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for (mask = SCSI_CTRL_RST; mask >= SCSI_CTRL_SEL; mask >>= 1) {
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if ((new_stat ^ this->bus_stat) & mask) {
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if (new_stat & mask)
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this->bus_obj->assert_ctrl_line(this->src_id, mask);
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else
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this->bus_obj->release_ctrl_line(this->src_id, mask);
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}
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}
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}
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this->bus_stat = new_stat;
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}
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void MeshController::step_completed() {
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this->int_stat |= INT_CMD_DONE;
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update_irq();
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}
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void MeshController::report_error(const int error) {
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switch(error) {
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case SEL_TIMEOUT:
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this->exception |= EXC_SEL_TIMEOUT;
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this->int_stat |= INT_EXCEPTION;
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break;
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default:
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ABORT_F("%s: unhandled error %d", this->name.c_str(), error);
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}
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this->int_stat |= INT_CMD_DONE;
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update_irq();
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}
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static const PropMap Mesh_properties = {
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{"hdd_img2", new StrProperty("")},
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{"cdr_img2", new StrProperty("")},
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};
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static const DeviceDescription Mesh_Tnt_Descriptor = {
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MeshController::create_for_tnt, {}, Mesh_properties
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};
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static const DeviceDescription Mesh_Heathrow_Descriptor = {
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MeshController::create_for_heathrow, {}, Mesh_properties
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};
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REGISTER_DEVICE(MeshTnt, Mesh_Tnt_Descriptor);
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REGISTER_DEVICE(MeshHeathrow, Mesh_Heathrow_Descriptor);
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